Simulation Results: gpio

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.09 %
  • code
  • 92.55 %
  • assert
  • 98.73 %
  • func
  • 100.00 %
  • line
  • 99.89 %
  • branch
  • 98.28 %
  • cond
  • 95.40 %
  • toggle
  • 94.19 %
  • FSM
  • 75.00 %
Validation stages
V1
99.22%
V2
92.24%
V2S
88.00%
V3
41.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 200 200 100.00
gpio_smoke 2.290s 324.102us 50 50 100.00
gpio_smoke_no_pullup_pulldown 2.340s 377.881us 50 50 100.00
gpio_smoke_en_cdc_prim 2.220s 311.283us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 2.450s 362.379us 50 50 100.00
csr_hw_reset 5 5 100.00
gpio_csr_hw_reset 1.140s 29.250us 5 5 100.00
csr_rw 20 20 100.00
gpio_csr_rw 1.210s 180.675us 20 20 100.00
csr_bit_bash 5 5 100.00
gpio_csr_bit_bash 6.320s 405.727us 5 5 100.00
csr_aliasing 3 5 60.00
gpio_csr_aliasing 2.260s 202.466us 3 5 60.00
csr_mem_rw_with_rand_reset 20 20 100.00
gpio_csr_mem_rw_with_rand_reset 1.720s 57.506us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 23 25 92.00
gpio_csr_rw 1.210s 180.675us 20 20 100.00
gpio_csr_aliasing 2.260s 202.466us 3 5 60.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 100 100 100.00
gpio_random_dout_din 2.150s 455.458us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 2.050s 135.955us 50 50 100.00
out_in_regs_read_write 50 50 100.00
gpio_dout_din_regs_random_rw 1.450s 135.467us 50 50 100.00
gpio_interrupt_programming 50 50 100.00
gpio_intr_rand_pgm 2.230s 409.603us 50 50 100.00
random_interrupt_trigger 50 50 100.00
gpio_rand_intr_trigger 5.580s 465.281us 50 50 100.00
interrupt_and_noise_filter 50 50 100.00
gpio_intr_with_filter_rand_intr_event 5.730s 400.986us 50 50 100.00
noise_filter_stress 50 50 100.00
gpio_filter_stress 21.740s 938.239us 50 50 100.00
regs_long_reads_and_writes 50 50 100.00
gpio_random_long_reg_writes_reg_reads 7.220s 1530.236us 50 50 100.00
full_random 50 50 100.00
gpio_full_random 1.760s 113.403us 50 50 100.00
stress_all 7 50 14.00
gpio_stress_all 177.080s 61068.113us 7 50 14.00
alert_test 50 50 100.00
gpio_alert_test 0.940s 44.378us 50 50 100.00
intr_test 50 50 100.00
gpio_intr_test 0.980s 30.395us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
gpio_tl_errors 4.320s 270.322us 20 20 100.00
tl_d_illegal_access 20 20 100.00
gpio_tl_errors 4.320s 270.322us 20 20 100.00
tl_d_outstanding_access 41 50 82.00
gpio_csr_rw 1.210s 180.675us 20 20 100.00
gpio_same_csr_outstanding 1.780s 589.801us 13 20 65.00
gpio_csr_aliasing 2.260s 202.466us 3 5 60.00
gpio_csr_hw_reset 1.140s 29.250us 5 5 100.00
tl_d_partial_access 41 50 82.00
gpio_csr_rw 1.210s 180.675us 20 20 100.00
gpio_same_csr_outstanding 1.780s 589.801us 13 20 65.00
gpio_csr_aliasing 2.260s 202.466us 3 5 60.00
gpio_csr_hw_reset 1.140s 29.250us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 22 25 88.00
gpio_tl_intg_err 3.280s 262.965us 17 20 85.00
gpio_sec_cm 1.330s 70.289us 5 5 100.00
sec_cm_bus_integrity 17 20 85.00
gpio_tl_intg_err 3.280s 262.965us 17 20 85.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 41 50 82.00
gpio_rand_straps 0.930s 47.912us 41 50 82.00
stress_all_with_rand_reset 0 50 0.00
gpio_stress_all_with_rand_reset 33.220s 2881.129us 0 50 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 50 50 100.00
gpio_inp_prd_cnt 0.970s 16.020us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (gpio_scoreboard.sv:248) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 52 test runs
gpio_stress_all 32404738057473257859574888027697788533542468638984195378641326794826502401504 748
UVM_INFO @ 1654536014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 71373079618988537579493480012799360200113955427492780197120467509594300787089 528
UVM_INFO @ 6767306797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 44841263011716830559071872460661530388164722042322974680318248638681923250710 80
UVM_INFO @ 751392662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 114622990431790675811205771692841110739421652768167126635072482682114677913032 362
UVM_INFO @ 1403175105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 47501558252312982342038274583439827831056986799264258993427873741380986519359 79
UVM_INFO @ 2283062967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 22230432138236164692325523507326225669138019006529383822953241066518597219330 2679
UVM_INFO @ 9703200521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 75672263475576117841113226433209827052902885953217346589998206825899484637462 1584
UVM_INFO @ 13869626281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 76034146737921833079295712861071774075995935157263796662699418856125186232227 76
UVM_INFO @ 2253532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 50812461052795499816111885315579098764369105791411307154685169087890802930007 80
UVM_INFO @ 467669034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 69244236808310340881620056463670840119065871235787972328904665461469256264880 75
UVM_INFO @ 1207593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 45099329351136126335752738029881194125304337673204860151377784784185438893002 2939
UVM_INFO @ 9523692252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 2926950809086905442921979517542255143823995845141588106837770641780592322389 1235
UVM_INFO @ 14471507557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 95028582124828986011471597118800054343854793982491550466669941583831439918190 176
UVM_INFO @ 7274200745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 2879773762186792250064939919108965058465494352126805509555531338872064246154 75
UVM_INFO @ 6856904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 112085484198884507523957365053247955002698197540489972469814276731524085169960 1391
UVM_INFO @ 4038195482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 47587653527744888129269967454976242392913784843600601337219547118468121618314 82
UVM_INFO @ 1890347436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 44004108668880053941434076017636510171412189696894199781800087736817568589241 105
UVM_INFO @ 971443620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 92322379683508659951404918711484190670313249291355063949220598225308795183330 2201
UVM_INFO @ 17529226558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 73540383748169398802093285039562676566937225570035778696361905123933366970939 3064
UVM_INFO @ 10803191854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 112373389744764863624769245538829801372231425961978508062274205328112002001193 160
UVM_INFO @ 4409846740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 67683378438539688911579662791834803134691420012725413651281470776550831627873 75
UVM_INFO @ 5363578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 103988605815614117723122191507727043858831368120848885013110285152756276125978 177
UVM_INFO @ 1883660118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 4143553568730829045163482636572782125834784650158545849835398888548739834284 1179
UVM_INFO @ 2519439014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 114162594337949933376718585281964207249366299901888126435619791194784318237106 251
UVM_INFO @ 2042232933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 12940291704670463055631444871256823266675806533462497923565913976998578875617 648
UVM_INFO @ 6226255640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 85402080441067655490175834373688059098329763248449524439831279114073329890458 325
UVM_INFO @ 1109099941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 10569257556504815542503935222832904045708796110431490629378179325546074636727 2835
UVM_INFO @ 36143127571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 65766415572763853541006964507728848024973539813835648126015846005353676836285 333
UVM_INFO @ 3396131411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 62885635784416450831539833946346218815023110030347827213446258693256975339706 75
UVM_INFO @ 1360496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 72210272937882373769116445372397963361342753251554914932556734774965128361528 262
UVM_INFO @ 1749475634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 30818351021801522402176594399843167999924755567774164409923898894811692539953 75
UVM_INFO @ 3895129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 84971053227754014744924338639202543426303580087938539099188889420270601892171 314
UVM_INFO @ 2325469995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 80522512829686360997922403472230199293716504415893473933158587388711824478582 77
UVM_INFO @ 215173825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 1738047559818045753527006358825839187884638162171818984172481456560223266636 946
UVM_INFO @ 2632732663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 110936679140858771504836337489616493788572416587326696994101214776900839270264 1176
UVM_INFO @ 3594675324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 87072411516953689953123240703974411959757265593235451594827123953120448608692 4328
UVM_INFO @ 61068113217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 90928064322448487345173936428717988794095169519217925816698426274386657560410 212
UVM_INFO @ 3280046901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 111117797261664753664158206300832570344202493151944695319511926034602250979973 75
UVM_INFO @ 1597190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 92880400977754708869613229801048569947477523216597607742892745093056128274967 1225
UVM_INFO @ 18954632697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 21905478307437813582332118551139800092361964598012784014299750344073888903699 1686
UVM_INFO @ 5513628029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 18982796788384463639234806041803526638884069030504056149718630146742594855165 298
UVM_INFO @ 1411183649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 45940077155772142229496023189975531907721686722630388632076705614613689441087 618
UVM_INFO @ 1028070363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 4206605492509602499720901184206757193099851467301871313973170398907649213950 2758
UVM_INFO @ 190767122740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 34310844536025215229935011976280289428138532246311776451530026956137262039491 467
UVM_INFO @ 2924492174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 109783637828210821217075591077636617593461861122748430690234733900055905572568 1025
UVM_INFO @ 4733349214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 69572546231947157305663114045790836773451899288602443985754697609283001758288 75
UVM_INFO @ 19430245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 61006850692244064403010871674684461357676543655621361678910544204561805820706 76
UVM_INFO @ 295759756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 33731573416401973792337586342224354422504687790980934550276227000788166564876 75
UVM_INFO @ 5452974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 70657000091522472757420835212099188192090059731366862922452020972190207680524 1591
UVM_INFO @ 6680751625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 110842328304975503529785428888035977213157694930805832056067127686945882105199 75
UVM_INFO @ 7100912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 12443020514923028132448534992948204119471424213850026218256142071541141931438 1222
UVM_INFO @ 3025165351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 31860230674964731909013870862740264064564032254459138377427558793901149126958 76
UVM_INFO @ 355131209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [gpio_common_vseq] Check failed (vseq_done) 31 test runs
gpio_stress_all_with_rand_reset 85135239420297862313930925303595996025395199201478057403946331031590490987899 80
UVM_INFO @ 11188085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 29561206758894295808935769679781455075632984690192723656377936538796963526326 80
UVM_INFO @ 9986555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 19398891905521768518011919621831419269328677703835543249743386633744833969158 681
UVM_INFO @ 2881128640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 38528164450611158600371698282148724237444860131965460737099719249071421266940 80
UVM_INFO @ 31471747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 101409132869645283833573407665090174899265340496150460639669352093262025929194 87
UVM_INFO @ 30550873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 6793744220584357782749395597397442546479688955438783639908299858943070517411 80
UVM_INFO @ 61510676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 95157062619398348672909914114560122623809215441199964010647345421977786762166 80
UVM_INFO @ 75828993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 35144245144207147662447600170105265362019263976385185622208930038484321229769 380
UVM_INFO @ 3745701379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 113485367099928082742334675448795228157414205548492051835933073114669079097406 80
UVM_INFO @ 176566910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 29134087598618530353123826547371863208928587637204143854405759455815162616485 80
UVM_INFO @ 6322819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 17928772426791699251940582061222593562488130179557164869170420405345898948307 80
UVM_INFO @ 21993606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 54643549976153415540835417439184714256823250603249161945944558108435255261510 80
UVM_INFO @ 7734425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 50744594593631216992263598224450258356895871330888462320723114192760337801862 80
UVM_INFO @ 4094347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 31919129761603955710930092432733920365144485070599558030960039780017529696632 80
UVM_INFO @ 11162630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 42416215605975196262216700000487311891984170913283009625782272354528747661433 80
UVM_INFO @ 29944988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 61627328557987478905636871571131938874479358945941918378583058901506645048603 114
UVM_INFO @ 8649112627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 102359503043719457131016958277231932389253321375633987252617108168302453435555 87
UVM_INFO @ 38941951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 15044082369131119088188715164778980039467180372721349740856931976817264581995 80
UVM_INFO @ 27293083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 54214200721883321354719712668716323086543642249436181327064611498171375823634 80
UVM_INFO @ 10318078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 57741082553087691433818161047828965950913601349610207028083200442164297864689 721
UVM_INFO @ 1736672509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 7003810051412180617178754753319881194269081501517883923577259242614804226713 100
UVM_INFO @ 309267662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 93055209119547060107783725609683366169938282096201230928051568668362937940891 94
UVM_INFO @ 91408877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 71913296579056453855677059748885193233469492717209154625618213626646119774681 289
UVM_INFO @ 11629523193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 77449772262497797971010181359915074533672387007691608454328248536278294676951 80
UVM_INFO @ 5253554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 113234262177076335635202289908563681290465875388959289717263483365668652516305 237
UVM_INFO @ 643786669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 13548690100883649646140168483823703921029739518815527779687906422932992356737 80
UVM_INFO @ 4506296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 56227796589674189763735149948223821177307560057444594705665379130409435287469 80
UVM_INFO @ 4930839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 111591888506823460803332644837856444975475954004096583547173560848490241218400 80
UVM_INFO @ 498645816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 39512823049521688635692514571457229321421569567585603003715576189652225577669 348
UVM_INFO @ 1426176032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 22333600449154307938304045186139908282701239477421030426210108945344928084555 80
UVM_INFO @ 14191608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 32532133425521734217550442345791901317232904821324662851869778632411763445663 81
UVM_INFO @ 1377910039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 19 test runs
gpio_stress_all_with_rand_reset 107397367886022355697194228134015871528689614228768725480144224322406568140649 78
UVM_INFO @ 6102540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 49684759719516331406162568278277986234250807485579033573430644637208979785144 79
UVM_INFO @ 903823672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 107428315529629187238140589368349696233278557601961523515462320146550568742749 78
UVM_INFO @ 20590713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 37920630260275700657042763654270767660487001438767649575797277151950531014557 78
UVM_INFO @ 13251420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 75277527568680513958698266077249948763859098979647137897082010195861303980942 78
UVM_INFO @ 1450447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 78025012524007493312475738145109273658488688051429815325040188998704565960416 81
UVM_INFO @ 420244609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 18148350426414974718395539809747650404726814551643059256055585768646208108781 80
UVM_INFO @ 437380641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 93711064613666772627675390507821644547950871711448148905937558683118836825400 78
UVM_INFO @ 3078499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 14835076093727019612256147474743767305431524674690249766845965141367300498033 468
UVM_INFO @ 423927638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 72494640599558677327016268212161538416524848375298408032199851526891271792992 78
UVM_INFO @ 15828321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 68683076824469133498851230274593804997842626987394471246792862507725890196851 80
UVM_INFO @ 199368558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 82100069114502468815808517991396650835153305301644881950661968675625451188208 80
UVM_INFO @ 172212443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 42718021961351466805722500164547988321844039904158162015261572262705348588198 78
UVM_INFO @ 1215487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 59406869704753853431953400923944944781313828039748140109096803100261936149737 79
UVM_INFO @ 353066113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 61834866790051960733355804149320993032528724341962617425211482511245813892773 78
UVM_INFO @ 19459529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 49384165892555813631074241530431793309921585367828159962186605956445176384688 81
UVM_INFO @ 930569684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 36461584606762136656772118795031301833543759262435921423574975452128308835104 78
UVM_INFO @ 3020375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 21586817173492831925779221263155500278004801993529982130635426380041767405888 78
UVM_INFO @ 5222659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 100141723514231855304651275256480018981296398151966635032773463756277668104948 78
UVM_INFO @ 37287948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 7 test runs
gpio_same_csr_outstanding 91620741587781087151139899242417485769949497692281200582749423087376505514727 76
UVM_INFO @ 23440846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 69799662498676208559196394322916433789349117334752647331529066905022046597255 77
UVM_INFO @ 25571971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 33591414190766234655454169785646647879694021755878311716783944178976481277553 77
UVM_INFO @ 7053242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 50579478400619383130103848914182706780639078522447482036307585790187659556412 77
UVM_INFO @ 513322252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 80196216233297738691578007945598213784981717765650038337202611241478473165088 77
UVM_INFO @ 40947979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 32035878199055629871940120455467047148328630904401832795693765285569133420989 78
UVM_INFO @ 358963388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 100158413790038774223862052433997490183471925613892190291741679545649500505512 76
UVM_INFO @ 33423199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_val_* reset value: * 2 test runs
gpio_csr_aliasing 93400258758466045048367980375356920600545382929912418209131004558259324907570 77
UVM_INFO @ 71030430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_csr_aliasing 558807656105495170468262698736689320591322485077916828648409396559731927020 78
UVM_INFO @ 202466145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_*.enable reset value: * 2 test runs
gpio_tl_intg_err 42937007835688527958220959214266360653817260315848248986027995425784220939390 220
UVM_INFO @ 395068804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_tl_intg_err 72760717880148259647215914273500062327647740229746971837539540486456028495673 84
UVM_INFO @ 52799799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_* reset value: * 1 test run
gpio_tl_intg_err 81134833224591971509059713385118084666086623495202078501360609737169295913281 353
UVM_INFO @ 1978786644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---