Simulation Results: hmac

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.99 %
  • code
  • 96.14 %
  • assert
  • 97.82 %
  • func
  • 100.00 %
  • block
  • 97.73 %
  • line
  • 98.44 %
  • branch
  • 94.35 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 18.000s 2541.098us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 2.000s 30.830us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 2.000s 20.906us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 17.000s 9482.899us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 7.000s 386.364us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 647.000s 153201.280us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 2.000s 20.906us 20 20 100.00
hmac_csr_aliasing 7.000s 386.364us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 124.000s 4123.240us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 97.000s 7062.278us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 314.000s 7784.759us 30 30 100.00
hmac_test_sha384_vectors 625.000s 30708.682us 75 75 100.00
hmac_test_sha512_vectors 664.000s 69320.584us 75 75 100.00
hmac_test_hmac256_vectors 20.000s 769.441us 50 50 100.00
hmac_test_hmac384_vectors 24.000s 830.453us 60 60 100.00
hmac_test_hmac512_vectors 25.000s 872.211us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 44.000s 813.920us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 439.000s 7095.834us 10 10 100.00
error 10 10 100.00
hmac_error 108.000s 4166.836us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 129.000s 2223.926us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 18.000s 2541.098us 10 10 100.00
hmac_long_msg 124.000s 4123.240us 10 10 100.00
hmac_back_pressure 97.000s 7062.278us 25 25 100.00
hmac_datapath_stress 439.000s 7095.834us 10 10 100.00
hmac_burst_wr 44.000s 813.920us 50 50 100.00
hmac_stress_all 960.000s 72984.857us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 18.000s 2541.098us 10 10 100.00
hmac_long_msg 124.000s 4123.240us 10 10 100.00
hmac_back_pressure 97.000s 7062.278us 25 25 100.00
hmac_datapath_stress 439.000s 7095.834us 10 10 100.00
hmac_wipe_secret 129.000s 2223.926us 10 10 100.00
hmac_test_sha256_vectors 314.000s 7784.759us 30 30 100.00
hmac_test_sha384_vectors 625.000s 30708.682us 75 75 100.00
hmac_test_sha512_vectors 664.000s 69320.584us 75 75 100.00
hmac_test_hmac256_vectors 20.000s 769.441us 50 50 100.00
hmac_test_hmac384_vectors 24.000s 830.453us 60 60 100.00
hmac_test_hmac512_vectors 25.000s 872.211us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 18.000s 2541.098us 10 10 100.00
hmac_long_msg 124.000s 4123.240us 10 10 100.00
hmac_back_pressure 97.000s 7062.278us 25 25 100.00
hmac_datapath_stress 439.000s 7095.834us 10 10 100.00
hmac_burst_wr 44.000s 813.920us 50 50 100.00
hmac_error 108.000s 4166.836us 10 10 100.00
hmac_wipe_secret 129.000s 2223.926us 10 10 100.00
hmac_test_sha256_vectors 314.000s 7784.759us 30 30 100.00
hmac_test_sha384_vectors 625.000s 30708.682us 75 75 100.00
hmac_test_sha512_vectors 664.000s 69320.584us 75 75 100.00
hmac_test_hmac256_vectors 20.000s 769.441us 50 50 100.00
hmac_test_hmac384_vectors 24.000s 830.453us 60 60 100.00
hmac_test_hmac512_vectors 25.000s 872.211us 75 75 100.00
hmac_stress_all 960.000s 72984.857us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 960.000s 72984.857us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 2.000s 20.993us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 2.000s 26.468us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 7.000s 939.719us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 7.000s 939.719us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 2.000s 30.830us 5 5 100.00
hmac_csr_rw 2.000s 20.906us 20 20 100.00
hmac_csr_aliasing 7.000s 386.364us 5 5 100.00
hmac_same_csr_outstanding 4.000s 153.253us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 2.000s 30.830us 5 5 100.00
hmac_csr_rw 2.000s 20.906us 20 20 100.00
hmac_csr_aliasing 7.000s 386.364us 5 5 100.00
hmac_same_csr_outstanding 4.000s 153.253us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 2.000s 85.706us 5 5 100.00
hmac_tl_intg_err 6.000s 1148.725us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 6.000s 1148.725us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 18.000s 2541.098us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.000s 127.590us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 1043.000s 122620.689us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 632.838us 1 1 100.00