Simulation Results: kmac/masked

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.03 %
  • code
  • 94.26 %
  • assert
  • 98.85 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.10 %
  • cond
  • 94.78 %
  • toggle
  • 99.89 %
  • FSM
  • 80.28 %
Validation stages
V1
100.00%
V2
99.35%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 75.810s 25461.731us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.330s 227.407us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.500s 110.428us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 18.170s 9776.326us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.470s 488.189us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.520s 171.265us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.500s 110.428us 20 20 100.00
kmac_csr_aliasing 7.470s 488.189us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.010s 13.366us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.470s 92.027us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 4985.430s 137703.821us 50 50 100.00
burst_write 49 50 98.00
kmac_burst_write 1319.040s 38959.332us 49 50 98.00
test_vectors 39 40 97.50
kmac_test_vectors_sha3_224 2933.710s 228058.723us 5 5 100.00
kmac_test_vectors_sha3_256 2663.480s 533624.173us 5 5 100.00
kmac_test_vectors_sha3_384 1796.280s 321547.273us 4 5 80.00
kmac_test_vectors_sha3_512 1335.360s 196619.418us 5 5 100.00
kmac_test_vectors_shake_128 3656.800s 126249.427us 5 5 100.00
kmac_test_vectors_shake_256 403.980s 55588.366us 5 5 100.00
kmac_test_vectors_kmac 3.050s 116.153us 5 5 100.00
kmac_test_vectors_kmac_xof 2.840s 249.047us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 519.540s 24773.445us 50 50 100.00
app 50 50 100.00
kmac_app 353.840s 36194.668us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 308.690s 33379.212us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 377.750s 22965.128us 50 50 100.00
error 48 50 96.00
kmac_error 403.210s 8668.121us 48 50 96.00
key_error 49 50 98.00
kmac_key_error 22.870s 19429.664us 49 50 98.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 8.940s 346.473us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 49.220s 2205.337us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 32.690s 9304.347us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 68.550s 7531.346us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 54.990s 1001.153us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 3248.170s 501514.352us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.190s 62.459us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.280s 137.943us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.620s 1392.136us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.620s 1392.136us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.330s 227.407us 5 5 100.00
kmac_csr_rw 1.500s 110.428us 20 20 100.00
kmac_csr_aliasing 7.470s 488.189us 5 5 100.00
kmac_same_csr_outstanding 3.190s 121.676us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.330s 227.407us 5 5 100.00
kmac_csr_rw 1.500s 110.428us 20 20 100.00
kmac_csr_aliasing 7.470s 488.189us 5 5 100.00
kmac_same_csr_outstanding 3.190s 121.676us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.930s 333.996us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.930s 333.996us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.930s 333.996us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.930s 333.996us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 5.480s 235.877us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_sec_cm 93.650s 11433.163us 5 5 100.00
kmac_tl_intg_err 5.720s 480.313us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.720s 480.313us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 54.990s 1001.153us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 75.810s 25461.731us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 519.540s 24773.445us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.930s 333.996us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 93.650s 11433.163us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 93.650s 11433.163us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 93.650s 11433.163us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 75.810s 25461.731us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 54.990s 1001.153us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 93.650s 11433.163us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 366.340s 93217.985us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 75.810s 25461.731us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 137.130s 11699.044us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:858) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 2 test runs
kmac_stress_all_with_rand_reset 105597585423507720361043492420438277001115321855820056125702906536905776005332 198
UVM_INFO @ 1081845201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 22681617296924050309884371834914350278190633010255729899673710618803835784881 227
UVM_INFO @ 5329355313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * 2 test runs
kmac_test_vectors_sha3_384 114468454442789209984175560904085025662802528672056698020673975440324846615332 78
UVM_INFO @ 25969556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_burst_write 90325992325525854041080387575661272883405642465670453781312465894271465721367 77
UVM_INFO @ 35104840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
kmac_error 7415840148023770536670008481737665880119408537585102627260872063374722391751 219
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 18918102163992206701958168848712501823943971577419388419523162070670074293733 185
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: * 1 test run
kmac_key_error 64067580619458922752782366158294830026154990099488387129984392078641638910656 77
UVM_INFO @ 29551562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---