Simulation Results: kmac/unmasked

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.91 %
  • code
  • 92.39 %
  • assert
  • 98.80 %
  • func
  • 96.54 %
  • line
  • 97.66 %
  • branch
  • 95.95 %
  • cond
  • 94.77 %
  • toggle
  • 100.00 %
  • FSM
  • 73.55 %
Validation stages
V1
100.00%
V2
96.49%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 71.190s 52404.478us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.540s 32.777us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.610s 112.937us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 23.130s 1423.862us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 9.580s 851.937us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.090s 343.445us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.610s 112.937us 20 20 100.00
kmac_csr_aliasing 9.580s 851.937us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.140s 13.679us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.910s 82.425us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 4162.350s 294553.518us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 951.510s 479343.783us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1528.650s 32729.057us 5 5 100.00
kmac_test_vectors_sha3_256 1996.950s 159984.207us 5 5 100.00
kmac_test_vectors_sha3_384 939.600s 52808.336us 5 5 100.00
kmac_test_vectors_sha3_512 1088.340s 218533.694us 5 5 100.00
kmac_test_vectors_shake_128 194.680s 28055.271us 5 5 100.00
kmac_test_vectors_shake_256 2410.300s 395026.646us 5 5 100.00
kmac_test_vectors_kmac 2.720s 42.641us 5 5 100.00
kmac_test_vectors_kmac_xof 2.920s 452.421us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 389.550s 48958.708us 50 50 100.00
app 50 50 100.00
kmac_app 328.760s 65416.919us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 269.270s 81392.454us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 350.640s 22141.722us 50 50 100.00
error 49 50 98.00
kmac_error 411.640s 88588.247us 49 50 98.00
key_error 49 50 98.00
kmac_key_error 12.600s 6157.259us 49 50 98.00
sideload_invalid 25 50 50.00
kmac_sideload_invalid 120.810s 10104.863us 25 50 50.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 39.440s 4238.231us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 38.320s 1772.913us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 52.610s 30846.657us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 53.450s 16579.824us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 3066.260s 2125227.882us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.220s 94.617us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.260s 22.793us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.510s 632.604us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.510s 632.604us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.540s 32.777us 5 5 100.00
kmac_csr_rw 1.610s 112.937us 20 20 100.00
kmac_csr_aliasing 9.580s 851.937us 5 5 100.00
kmac_same_csr_outstanding 3.570s 444.030us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.540s 32.777us 5 5 100.00
kmac_csr_rw 1.610s 112.937us 20 20 100.00
kmac_csr_aliasing 9.580s 851.937us 5 5 100.00
kmac_same_csr_outstanding 3.570s 444.030us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.460s 89.613us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.460s 89.613us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.460s 89.613us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.460s 89.613us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 5.990s 1176.410us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_sec_cm 74.500s 24663.729us 5 5 100.00
kmac_tl_intg_err 6.330s 2543.718us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 6.330s 2543.718us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 53.450s 16579.824us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 71.190s 52404.478us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 389.550s 48958.708us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.460s 89.613us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 74.500s 24663.729us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 74.500s 24663.729us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 74.500s 24663.729us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 71.190s 52404.478us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 53.450s 16579.824us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 74.500s 24663.729us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 228.720s 15300.773us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 71.190s 52404.478us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
kmac_stress_all_with_rand_reset 295.440s 9273.373us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
kmac_stress_all_with_rand_reset 62255164012456803416660333057633177876259775007251919310209950728371393097496 197
UVM_INFO @ 7098419942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 110852923450974640750263602002777030547911841339076718713471653608921146327137 191
UVM_INFO @ 3462669948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 37841294898026306037857503872270727143517587428560421845681955335017982639418 127
UVM_INFO @ 3284963942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 59956618832783389551599929642386872253827529662545518531157583028380249564443 184
UVM_INFO @ 2303295574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 54702424673541870959985845175601276174521459162525120039060261034478508357772 173
UVM_INFO @ 3436680985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 5 test runs
kmac_sideload_invalid 96296258725729365596324591249924422624509511291965318453381395521702179569577 78
UVM_INFO @ 10036211907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 78047663613743512968676185589648293300023591084067310001555831760563628276326 78
UVM_INFO @ 10008772847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 5489258963123905069506474305675068315996256695070484042254644043951743420140 78
UVM_INFO @ 10009004685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 46785455168630174607131772250671389901842082510098462299761411390317569493740 78
UVM_INFO @ 10149123184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 91601076630305840412106045038469130876732171692931285481346616886058767920929 78
UVM_INFO @ 10008601344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) 3 test runs
kmac_sideload_invalid 34199730400702996440721732703638146841469078485128982119357818189621138468590 79
UVM_INFO @ 10265742881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 58168559238010128089706260718910707413356240235302377988463889222132440774613 79
UVM_INFO @ 10080550847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 107638856250376202362216528809996160661982072930192737357806856204791542593642 79
UVM_INFO @ 10101284133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) 2 test runs
kmac_sideload_invalid 87141942122733248198896851547464167214944846827835738824800791360219357154832 92
UVM_INFO @ 10786487532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 31704248417518503066389441164872156546690813665509885577498776269158179237870 91
UVM_INFO @ 10098562814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) 2 test runs
kmac_sideload_invalid 90604586053556549760411417930891445272174891802123261932382293585163063539155 86
UVM_INFO @ 10601836913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 45628671455649730152933490005649597102995725124766729424157648716088197750220 86
UVM_INFO @ 10803786421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) 2 test runs
kmac_sideload_invalid 102412353983985781412597243476397744378520454853435290703522379712425844050938 81
UVM_INFO @ 10049718804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 14778704530239012264944451626786628517997378488479959533934592651242282919107 81
UVM_INFO @ 10117943115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) 2 test runs
kmac_sideload_invalid 11096904940160661424841769023442427592054491079015930064668094252698639127990 82
UVM_INFO @ 10071489516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 37299474136289891859062282541764744573889216620689082895687873220112827233083 83
UVM_INFO @ 10058755484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) 2 test runs
kmac_sideload_invalid 2287355600902027654272493289902348200032365346836027679752756718877580929969 94
UVM_INFO @ 10095550505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 38189036595637448345001822402216669016119450963384715946812530947470921577196 93
UVM_INFO @ 10104863214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) 1 test run
kmac_sideload_invalid 73784330459350471674852491814890690330439075059403987605780347352516177929194 90
UVM_INFO @ 10098775428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) 1 test run
kmac_sideload_invalid 68076197848480116011667893719511810242599191254254704319519174175403278578630 84
UVM_INFO @ 10163698177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) 1 test run
kmac_sideload_invalid 20235039176754016111837346224259765908967043104165907953456423411408865884575 99
UVM_INFO @ 11497403871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
kmac_error 6703461961267965018758788536321552921895171786249989121083857987019043726318 160
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) 1 test run
kmac_sideload_invalid 78999571595340510686481286058831831047160581072245982910194019843113289074446 87
UVM_INFO @ 10159884912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) 1 test run
kmac_sideload_invalid 97243632682122203184902057904721605068578895990967354543299106073844340010085 84
UVM_INFO @ 10036240276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) 1 test run
kmac_sideload_invalid 81047723594848520909544699325468421540489663714826925068834238659972389212032 94
UVM_INFO @ 12018327444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) 1 test run
kmac_sideload_invalid 70851544293354058699045752567494310389487973613436812219230691200817188093980 96
UVM_INFO @ 10198874528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! 1 test run
kmac_key_error 5780844165549428565070169184835971652088987093890843013610825618266643358343 101
UVM_INFO @ 6067416483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---