Simulation Results: lc_ctrl/volatile_unlock_disabled

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.51 %
  • code
  • 93.58 %
  • assert
  • 96.83 %
  • func
  • 90.13 %
  • block
  • 96.75 %
  • line
  • 97.38 %
  • branch
  • 91.72 %
  • toggle
  • 89.97 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.04%
V2S
99.72%
V3
58.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 5.000s 84.966us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 19.000s 39.491us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 18.000s 85.419us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 23.000s 96.119us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 20.000s 129.100us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 19.000s 22.442us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 18.000s 85.419us 20 20 100.00
lc_ctrl_csr_aliasing 20.000s 129.100us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 4.000s 243.926us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 19.000s 3539.462us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 20.000s 18.997us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 6.000s 746.358us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 10.000s 2584.990us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 22.000s 301.449us 50 50 100.00
security_escalation 256 260 98.46
lc_ctrl_state_failure 10.000s 2584.990us 50 50 100.00
lc_ctrl_prog_failure 6.000s 746.358us 50 50 100.00
lc_ctrl_errors 22.000s 301.449us 50 50 100.00
lc_ctrl_security_escalation 11.000s 391.047us 50 50 100.00
lc_ctrl_jtag_state_failure 55.000s 5855.644us 19 20 95.00
lc_ctrl_jtag_prog_failure 20.000s 1513.715us 17 20 85.00
lc_ctrl_jtag_errors 54.000s 6808.305us 20 20 100.00
jtag_access 206 210 98.10
lc_ctrl_jtag_smoke 9.000s 1654.586us 20 20 100.00
lc_ctrl_jtag_state_post_trans 18.000s 1861.169us 19 20 95.00
lc_ctrl_jtag_prog_failure 20.000s 1513.715us 17 20 85.00
lc_ctrl_jtag_errors 54.000s 6808.305us 20 20 100.00
lc_ctrl_jtag_access 22.000s 2054.028us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 17.000s 1046.913us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 486.137us 10 10 100.00
lc_ctrl_jtag_csr_rw 6.000s 199.050us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 33.000s 9156.313us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 17.000s 3124.510us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 197.036us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 202.466us 10 10 100.00
lc_ctrl_jtag_alert_test 10.000s 68.698us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 71.000s 20581.176us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 13.565us 50 50 100.00
stress_all 48 50 96.00
lc_ctrl_stress_all 360.000s 182924.955us 48 50 96.00
alert_test 50 50 100.00
lc_ctrl_alert_test 20.000s 65.920us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 6.000s 506.484us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 6.000s 506.484us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 19.000s 39.491us 5 5 100.00
lc_ctrl_csr_rw 18.000s 85.419us 20 20 100.00
lc_ctrl_csr_aliasing 20.000s 129.100us 5 5 100.00
lc_ctrl_same_csr_outstanding 3.000s 50.910us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 19.000s 39.491us 5 5 100.00
lc_ctrl_csr_rw 18.000s 85.419us 20 20 100.00
lc_ctrl_csr_aliasing 20.000s 129.100us 5 5 100.00
lc_ctrl_same_csr_outstanding 3.000s 50.910us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 11.000s 1623.488us 5 5 100.00
lc_ctrl_tl_intg_err 5.000s 4189.623us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 5.000s 4189.623us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 19.000s 3539.462us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 10.000s 2584.990us 50 50 100.00
lc_ctrl_sec_cm 11.000s 1623.488us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 10.000s 2584.990us 50 50 100.00
lc_ctrl_sec_cm 11.000s 1623.488us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 10.000s 2584.990us 50 50 100.00
lc_ctrl_sec_cm 11.000s 1623.488us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 10.000s 2584.990us 50 50 100.00
lc_ctrl_sec_cm 11.000s 1623.488us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 10.000s 2584.990us 50 50 100.00
lc_ctrl_sec_cm 11.000s 1623.488us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 10.000s 2584.990us 50 50 100.00
lc_ctrl_sec_cm 11.000s 1623.488us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 10.000s 2584.990us 50 50 100.00
lc_ctrl_sec_cm 11.000s 1623.488us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 10.000s 2584.990us 50 50 100.00
lc_ctrl_sec_cm 11.000s 1623.488us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 11.000s 391.047us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 69 70 98.57
lc_ctrl_state_post_trans 4.000s 243.926us 50 50 100.00
lc_ctrl_jtag_state_post_trans 18.000s 1861.169us 19 20 95.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 11.000s 2117.065us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 11.000s 2117.065us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 17.000s 1397.741us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 15.000s 3162.879us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 15.000s 3162.879us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 29 50 58.00
lc_ctrl_stress_all_with_rand_reset 96.000s 30520.332us 29 50 58.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 19 test runs
lc_ctrl_stress_all_with_rand_reset 72817441069837417139117908219885375618845309112566661279069121493764123386757 276
UVM_INFO @ 464032884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108379796477480715348317337027323285818831257986169304273431687266146238110077 181
UVM_INFO @ 854636088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 33242212884323787778248911458147754110363455636234896501933931349770645331202 478
UVM_INFO @ 9779913235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 40153187009622479471459966836164750787820658618576208763928502624778113379902 2061
UVM_INFO @ 2698320619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 99270522762407849473645570419502877628775259375216697309571018825965764460508 1196
UVM_INFO @ 590593693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 62715396607840918810821513888208177263754629578788997143504877636157058083825 2041
UVM_INFO @ 3815797091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 46708677890658220058880755233318080591442875926716590426577506186593335574847 5474
UVM_INFO @ 10281654350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 90440102443612030194313823338604826788163911078296892478931933019523994484704 5058
UVM_INFO @ 28002526949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14861699979498910146044119265241156816818508120507022773238533649188108195315 160
UVM_INFO @ 227201312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 39108971708966355537161913940485170195797491835054001253751590672575601372805 2442
UVM_INFO @ 6115408972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 55490130313646705621601701203796203842489088667188767269126692707324123123510 280
UVM_INFO @ 8729053641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 24414916895320509907410257295727595456001757068184165048273944486375994210177 2173
UVM_INFO @ 2830094319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 83879528598242051413294552666759323277507930602505537135546082373813037937269 1176
UVM_INFO @ 5487573381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 26497440698785933604822762208897668072889693031554086324204145133251284181927 1231
UVM_INFO @ 19843694697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 31507637271207319615120661500546712986078781714807612640851964302471587252695 164
UVM_INFO @ 608923592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 11430941652447230247081311883355267509811882521658686266853778446519342652656 1711
UVM_INFO @ 3511444872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 8735504648469824299285766846879874378228309293675690064568822990578435744421 1202
UVM_INFO @ 7222163823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 59715079259518031232042407804765667318263318952080528920382286742295882810298 275
UVM_INFO @ 950053460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 110350353864721939874565846101353654542851843396506516320714545584262764797577 2688
UVM_INFO @ 3404575098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 3 test runs
lc_ctrl_jtag_prog_failure 21666118308082205006259094974849836773380757394089186813762102365167912755357 179
UVM_INFO @ 85358703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 40705865564483522376919642574226165660980081249912680855491205421699737745090 178
UVM_INFO @ 84598709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 82038089513470825849811416525812730948297850905896573590897973615840822119550 177
UVM_INFO @ 158124407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_state_post_trans 80635997054155727538773225376992816933030248669784856031448952884027597079971 180
UVM_INFO @ 209291962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 51934473833477765375366528593485661286957165726497387288936248372921684633597 177
UVM_INFO @ 22943060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* 2 test runs
lc_ctrl_stress_all 5805651950773767604062462464269645350009862062807092353898211678841980425539 6808
UVM_INFO @ 26407847895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 112731216135922685388582843246515008905283872723212596592973238098377035902563 6903
UVM_INFO @ 30960572641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 2 test runs
lc_ctrl_stress_all_with_rand_reset 103565620889066831488040309519112260943492219705583887840007164259041813047592 1063
UVM_INFO @ 1749996386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 45673539697251600863796465521410722241697405085832991840736669605313678150 4032
UVM_INFO @ 39163095422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---