Simulation Results: lc_ctrl/volatile_unlock_enabled

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.85 %
  • code
  • 94.59 %
  • assert
  • 96.83 %
  • func
  • 90.13 %
  • block
  • 97.25 %
  • line
  • 97.72 %
  • branch
  • 93.02 %
  • toggle
  • 89.99 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
99.59%
V2S
99.72%
V3
52.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 6.000s 190.130us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 2.000s 203.593us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 2.000s 117.596us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 3.000s 62.025us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 3.000s 171.964us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 3.000s 32.985us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 2.000s 117.596us 20 20 100.00
lc_ctrl_csr_aliasing 3.000s 171.964us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 4.000s 79.947us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 13.000s 4478.214us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 2.000s 14.558us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.000s 84.822us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 9.000s 424.969us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 15.000s 767.954us 50 50 100.00
security_escalation 258 260 99.23
lc_ctrl_state_failure 9.000s 424.969us 50 50 100.00
lc_ctrl_prog_failure 4.000s 84.822us 50 50 100.00
lc_ctrl_errors 15.000s 767.954us 50 50 100.00
lc_ctrl_security_escalation 12.000s 1188.528us 50 50 100.00
lc_ctrl_jtag_state_failure 58.000s 12685.544us 18 20 90.00
lc_ctrl_jtag_prog_failure 14.000s 8232.320us 20 20 100.00
lc_ctrl_jtag_errors 72.000s 4469.412us 20 20 100.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 15.000s 3864.557us 20 20 100.00
lc_ctrl_jtag_state_post_trans 16.000s 7298.251us 19 20 95.00
lc_ctrl_jtag_prog_failure 14.000s 8232.320us 20 20 100.00
lc_ctrl_jtag_errors 72.000s 4469.412us 20 20 100.00
lc_ctrl_jtag_access 16.000s 871.000us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 22.000s 2632.994us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 235.480us 10 10 100.00
lc_ctrl_jtag_csr_rw 4.000s 697.565us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 27.000s 3122.907us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 13.000s 1344.207us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 50.519us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 210.520us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 83.153us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 21.000s 2445.542us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 3.000s 43.856us 50 50 100.00
stress_all 50 50 100.00
lc_ctrl_stress_all 250.000s 46130.564us 50 50 100.00
alert_test 50 50 100.00
lc_ctrl_alert_test 3.000s 44.916us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 4.000s 537.239us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 4.000s 537.239us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 2.000s 203.593us 5 5 100.00
lc_ctrl_csr_rw 2.000s 117.596us 20 20 100.00
lc_ctrl_csr_aliasing 3.000s 171.964us 5 5 100.00
lc_ctrl_same_csr_outstanding 3.000s 82.157us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 2.000s 203.593us 5 5 100.00
lc_ctrl_csr_rw 2.000s 117.596us 20 20 100.00
lc_ctrl_csr_aliasing 3.000s 171.964us 5 5 100.00
lc_ctrl_same_csr_outstanding 3.000s 82.157us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 5.000s 247.229us 5 5 100.00
lc_ctrl_tl_intg_err 3.000s 129.445us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 3.000s 129.445us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 13.000s 4478.214us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 9.000s 424.969us 50 50 100.00
lc_ctrl_sec_cm 5.000s 247.229us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 9.000s 424.969us 50 50 100.00
lc_ctrl_sec_cm 5.000s 247.229us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 9.000s 424.969us 50 50 100.00
lc_ctrl_sec_cm 5.000s 247.229us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 9.000s 424.969us 50 50 100.00
lc_ctrl_sec_cm 5.000s 247.229us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 9.000s 424.969us 50 50 100.00
lc_ctrl_sec_cm 5.000s 247.229us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 9.000s 424.969us 50 50 100.00
lc_ctrl_sec_cm 5.000s 247.229us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 9.000s 424.969us 50 50 100.00
lc_ctrl_sec_cm 5.000s 247.229us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 9.000s 424.969us 50 50 100.00
lc_ctrl_sec_cm 5.000s 247.229us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 12.000s 1188.528us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 69 70 98.57
lc_ctrl_state_post_trans 4.000s 79.947us 50 50 100.00
lc_ctrl_jtag_state_post_trans 16.000s 7298.251us 19 20 95.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 12.000s 464.215us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 12.000s 464.215us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 12.000s 4192.665us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 11.000s 1366.846us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 11.000s 1366.846us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 26 50 52.00
lc_ctrl_stress_all_with_rand_reset 154.000s 111227.483us 26 50 52.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 21 test runs
lc_ctrl_stress_all_with_rand_reset 28491923823919529873346195564129566640022019956050438900614532819944701450799 2202
UVM_INFO @ 1272007105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 64166015402036946762770237633174164611292091194595579664645979926911840530108 173
UVM_INFO @ 1639488141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 54766748224034716690899360473393158260306657761212678580225706015682335485489 2291
UVM_INFO @ 8908457584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 18760100627539207706620831905285101955396210632023424632664771938129687143031 405
UVM_INFO @ 1165837231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 20910230069707544592013784614999127530745114875567784220372249721329312414263 160
UVM_INFO @ 216050368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 60385214367512177690884921039519849185614661727525580794168377682250855457973 2950
UVM_INFO @ 2734812506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 64024037572915796265700869841573774456324142240127856214666680925377253067888 2184
UVM_INFO @ 3050032791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 68738789113690505616493818966447749059821306252208872260077677480741524537735 2379
UVM_INFO @ 3145892036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 43901891708598169901008466330176530525728151186297952047259749189672345120624 165
UVM_INFO @ 284721695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 27403670723376135294909514639979930365978314692639772035200086328604186674657 160
UVM_INFO @ 105273637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 42578437081301806995744764304450802783240895550580826697147880411752373311129 1950
UVM_INFO @ 3375207381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 38530984445656690798098527650515902058468469370695272008941472716889454270443 202
UVM_INFO @ 2342306431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 86255865442066116874567312667223088300676160366140499839639638676971752847324 2775
UVM_INFO @ 9472377501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 15928055667393378703464335406285992208815878017328653691086544870821966948915 198
UVM_INFO @ 593728408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 79602916157992155879574539024974934576527791105835509037995687396888751790961 850
UVM_INFO @ 2429006465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 61554847570402187348405491202561844349115777120459859948419493372134824608962 1099
UVM_INFO @ 1926666826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 90845037471520600824114237127737273023583560341087944960457239504820015975173 2291
UVM_INFO @ 7462390282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 18862613226996335110958623380693602482551450058776596899490835086103244063577 188
UVM_INFO @ 713739522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 78561983475631988463115980251644732892067392080594790792496605191914294381787 161
UVM_INFO @ 218700613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 35651583100886709196931061366011611563470132471008094129703386096972675720864 308
UVM_INFO @ 3647417198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 72022181382697903264071760893538826489143141648977550001595563865311345001702 182
UVM_INFO @ 231430221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 3 test runs
lc_ctrl_jtag_state_failure 84729598059887254165123271953180172916246082742212039528729058500667002255238 177
UVM_INFO @ 368974894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 17057076431897877218130697957165216728552499540992344269592997300019052752483 179
UVM_INFO @ 226981824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 113658155573762745514772056717405251601310204026150731302052265989723683377761 177
UVM_INFO @ 426568884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 2 test runs
lc_ctrl_stress_all_with_rand_reset 87637864604268657709262620451486923003303598858301765007654106324700184400096 2596
UVM_INFO @ 1532383900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 24128579034649646778984806226485357117986133455980671196776775611770717971987 1211
UVM_INFO @ 2168086265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* 1 test run
lc_ctrl_stress_all_with_rand_reset 56019636468667458184919008128860583005564552221584045216113619858233918757950 828
UVM_INFO @ 676451469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---