Simulation Results: otbn

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.61 %
  • code
  • 95.65 %
  • assert
  • 91.17 %
  • func
  • 100.00 %
  • block
  • 99.46 %
  • line
  • 99.60 %
  • branch
  • 93.10 %
  • toggle
  • 89.89 %
  • FSM
  • 100.00 %
Validation stages
V1
99.40%
V2
98.19%
V2S
97.64%
V3
50.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 64.476us 1 1 100.00
single_binary 99 100 99.00
otbn_single 101.000s 1704.325us 99 100 99.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 8.000s 138.693us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 8.000s 48.140us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 10.000s 657.466us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 8.000s 23.668us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 9.000s 30.429us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 8.000s 48.140us 20 20 100.00
otbn_csr_aliasing 8.000s 23.668us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 153.000s 37158.461us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 52.000s 5472.765us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 51.000s 190.303us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 63.000s 948.909us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 156.000s 387.448us 10 10 100.00
stress_all 8 10 80.00
otbn_stress_all 128.000s 565.147us 8 10 80.00
lc_escalation 58 60 96.67
otbn_escalate 26.000s 383.745us 58 60 96.67
zero_state_err_urnd 4 5 80.00
otbn_zero_state_err_urnd 7.000s 45.897us 4 5 80.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 19.000s 159.489us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 8.000s 99.741us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 7.000s 52.906us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 10.000s 459.365us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 10.000s 459.365us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 8.000s 138.693us 5 5 100.00
otbn_csr_rw 8.000s 48.140us 20 20 100.00
otbn_csr_aliasing 8.000s 23.668us 5 5 100.00
otbn_same_csr_outstanding 7.000s 48.863us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 8.000s 138.693us 5 5 100.00
otbn_csr_rw 8.000s 48.140us 20 20 100.00
otbn_csr_aliasing 8.000s 23.668us 5 5 100.00
otbn_same_csr_outstanding 7.000s 48.863us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 26.000s 92.391us 10 10 100.00
otbn_dmem_err 15.000s 41.367us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 9.000s 484.850us 5 5 100.00
otbn_controller_ispr_rdata_err 11.000s 201.657us 5 5 100.00
otbn_mac_bignum_acc_err 12.000s 234.038us 5 5 100.00
otbn_urnd_err 10.000s 117.658us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 8.000s 22.122us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 7.000s 27.138us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 7.000s 20.328us 9 10 90.00
tl_intg_err 25 25 100.00
otbn_sec_cm 262.000s 11230.152us 5 5 100.00
otbn_tl_intg_err 41.000s 231.845us 20 20 100.00
passthru_mem_tl_intg_err 19 20 95.00
otbn_passthru_mem_tl_intg_err 65.000s 250.601us 19 20 95.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 262.000s 11230.152us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 262.000s 11230.152us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 64.476us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 15.000s 41.367us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 26.000s 92.391us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 41.000s 231.845us 20 20 100.00
sec_cm_controller_fsm_global_esc 58 60 96.67
otbn_escalate 26.000s 383.745us 58 60 96.67
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 26.000s 92.391us 10 10 100.00
otbn_dmem_err 15.000s 41.367us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 45.897us 4 5 80.00
otbn_illegal_mem_acc 8.000s 22.122us 5 5 100.00
otbn_sec_cm 262.000s 11230.152us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 262.000s 11230.152us 5 5 100.00
sec_cm_scramble_key_sideload 99 100 99.00
otbn_single 101.000s 1704.325us 99 100 99.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 26.000s 92.391us 10 10 100.00
otbn_dmem_err 15.000s 41.367us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 45.897us 4 5 80.00
otbn_illegal_mem_acc 8.000s 22.122us 5 5 100.00
otbn_sec_cm 262.000s 11230.152us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 262.000s 11230.152us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 58 60 96.67
otbn_escalate 26.000s 383.745us 58 60 96.67
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 26.000s 92.391us 10 10 100.00
otbn_dmem_err 15.000s 41.367us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 45.897us 4 5 80.00
otbn_illegal_mem_acc 8.000s 22.122us 5 5 100.00
otbn_sec_cm 262.000s 11230.152us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 262.000s 11230.152us 5 5 100.00
sec_cm_data_reg_sw_sca 99 100 99.00
otbn_single 101.000s 1704.325us 99 100 99.00
sec_cm_ctrl_redun 11 12 91.67
otbn_ctrl_redun 10.000s 32.592us 11 12 91.67
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 9.000s 26.930us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 131.000s 346.085us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 131.000s 346.085us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 24.000s 88.655us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 262.000s 11230.152us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 262.000s 11230.152us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 12.000s 61.101us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 262.000s 11230.152us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 262.000s 11230.152us 5 5 100.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 13.000s 25.758us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 13.000s 25.758us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 21.000s 42.950us 7 7 100.00
sec_cm_data_mem_sec_wipe 99 100 99.00
otbn_single 101.000s 1704.325us 99 100 99.00
sec_cm_instruction_mem_sec_wipe 99 100 99.00
otbn_single 101.000s 1704.325us 99 100 99.00
sec_cm_data_reg_sw_sec_wipe 99 100 99.00
otbn_single 101.000s 1704.325us 99 100 99.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 156.000s 387.448us 10 10 100.00
sec_cm_ctrl_flow_count 99 100 99.00
otbn_single 101.000s 1704.325us 99 100 99.00
sec_cm_ctrl_flow_sca 99 100 99.00
otbn_single 101.000s 1704.325us 99 100 99.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 16.000s 83.649us 5 5 100.00
sec_cm_key_sideload 99 100 99.00
otbn_single 101.000s 1704.325us 99 100 99.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 262.000s 11230.152us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
otbn_stress_all_with_rand_reset 394.000s 3865.139us 5 10 50.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 34.435us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 4 test runs
otbn_zero_state_err_urnd 29186130167608750228568837615908809089469525994405518570796369949240427916114 156
UVM_ERROR @ 22935711 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 22935711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stack_addr_integ_chk 54488078238759381875788996308825262939760336902552108451830924272045232634637 121
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 5707056 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 5707056 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 5707056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_ctrl_redun 62057307011156635793056742121724020583217124426227240240822514980544028968321 111
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,1194): (time 9195865 PS) Assertion tb.dut.u_otbn_core.OnlyWriteLoadDataBignumWhenDMemValid_A has failed
UVM_ERROR @ 9195865 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 9195865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 88221919926455575100461670678466650425832521952535184695830707283792703479363 110
UVM_ERROR @ 50411743 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 50411743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
otbn_stress_all_with_rand_reset 31869769915487800266845677315050791791440299698942521749770186952695370401775 345
UVM_INFO @ 2602734271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 12689551093877427818178013368899601783671661004813245662166674397543427792919 235
UVM_INFO @ 846569335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 23907045840103903960933588672740502964708095234680164959551901060147365356345 207
UVM_INFO @ 441437271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
otbn_stress_all 81876369696104414429242530356735350606825319139968623132721662358185569989661 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
otbn_single 2935549720194794733203235978282009482803278057387334777417374751752256235804 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 23636760926833575667568069418660416435624275208285284951219191646826543117921 111
UVM_INFO @ 82656322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_partial_wipe 84558611925034707370268767946353296582218690119393672638357449475048464849932 107
UVM_ERROR @ 20327778 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 20327778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_stress_all 23713951622411746381553013715320760894830084005563376329627351566703957926949 152
UVM_INFO @ 34375761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 37756399607782963692718226520214402245099025813990147523850911571382309716743 573
UVM_INFO @ 665796152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 82968274071852916271539215269857757925185332684302608623560647589766652178055 411
UVM_INFO @ 905342061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:507) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. 1 test run
otbn_escalate 94807683666962400108377013664158225630108154831725680331885856039710069225751 107
UVM_INFO @ 44156756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---