Simulation Results: rom_ctrl/64kb

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.19 %
  • code
  • 94.62 %
  • assert
  • 97.67 %
  • func
  • 99.29 %
  • block
  • 96.73 %
  • line
  • 97.22 %
  • branch
  • 94.09 %
  • toggle
  • 87.16 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
85.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 7.000s 400.445us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 11.000s 1122.120us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 11.000s 4143.823us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 8.000s 302.028us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 7.000s 545.317us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 9.000s 294.875us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 11.000s 4143.823us 20 20 100.00
rom_ctrl_csr_aliasing 7.000s 545.317us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 7.000s 1933.800us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 9.000s 1029.528us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 9.000s 310.300us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 33.000s 2160.880us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 16.000s 5502.184us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 10.000s 1039.861us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 10.000s 546.330us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 10.000s 546.330us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 11.000s 1122.120us 5 5 100.00
rom_ctrl_csr_rw 11.000s 4143.823us 20 20 100.00
rom_ctrl_csr_aliasing 7.000s 545.317us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.000s 2054.451us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 11.000s 1122.120us 5 5 100.00
rom_ctrl_csr_rw 11.000s 4143.823us 20 20 100.00
rom_ctrl_csr_aliasing 7.000s 545.317us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.000s 2054.451us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.000s 24325.585us 20 20 100.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 35.000s 1636.572us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 255.000s 1524.320us 5 5 100.00
rom_ctrl_tl_intg_err 56.000s 887.835us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 255.000s 1524.320us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 255.000s 1524.320us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.000s 24325.585us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.000s 24325.585us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.000s 24325.585us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.000s 24325.585us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.000s 24325.585us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 255.000s 1524.320us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 255.000s 1524.320us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 7.000s 400.445us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 7.000s 400.445us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 7.000s 400.445us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 56.000s 887.835us 20 20 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.000s 24325.585us 20 20 100.00
rom_ctrl_kmac_err_chk 16.000s 5502.184us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.000s 24325.585us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.000s 24325.585us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.000s 24325.585us 20 20 100.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 35.000s 1636.572us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 255.000s 1524.320us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 17 20 85.00
rom_ctrl_stress_all_with_rand_reset 152.000s 24780.933us 17 20 85.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 3 test runs
rom_ctrl_stress_all_with_rand_reset 39409941227548762608407041821962469972380261106107507066291072910447612273832 92
UVM_INFO @ 1721406808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 59506070888954231750877340679997438865484749672218645037567017873720383102768 92
UVM_INFO @ 1982677856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 102525287470973314482508915260076239861817973660705110310797791326493655350307 91
UVM_INFO @ 172497134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---