Simulation Results: rstmgr

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.93 %
  • code
  • 99.59 %
  • assert
  • 98.72 %
  • func
  • 98.49 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.43 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.46%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.790s 69.146us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 1.360s 64.572us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 1.250s 38.259us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 3.450s 127.463us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 1.580s 38.002us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.840s 94.851us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 1.250s 38.259us 20 20 100.00
rstmgr_csr_aliasing 1.580s 38.002us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 2.150s 151.046us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 1.520s 37.846us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.640s 79.695us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 8.710s 1025.674us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 8.710s 1025.674us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 8.710s 1025.674us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 8.710s 1025.674us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 54.320s 6699.000us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.670s 151.207us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 2.540s 78.171us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 2.540s 78.171us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 1.360s 64.572us 5 5 100.00
rstmgr_csr_rw 1.250s 38.259us 20 20 100.00
rstmgr_csr_aliasing 1.580s 38.002us 5 5 100.00
rstmgr_same_csr_outstanding 1.600s 66.322us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 1.360s 64.572us 5 5 100.00
rstmgr_csr_rw 1.250s 38.259us 20 20 100.00
rstmgr_csr_aliasing 1.580s 38.002us 5 5 100.00
rstmgr_same_csr_outstanding 1.600s 66.322us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_sec_cm 18.500s 3396.585us 5 5 100.00
rstmgr_tl_intg_err 4.810s 631.968us 20 20 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 18.500s 3396.585us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 18.500s 3396.585us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 4.810s 631.968us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.750s 68.068us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 47 50 94.00
rstmgr_leaf_rst_cnsty 6.670s 479.168us 47 50 94.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 3.640s 292.106us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 18.500s 3396.585us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 1.250s 38.259us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 1.250s 38.259us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:* 3 test runs
rstmgr_leaf_rst_cnsty 39785242163212121972434055446106681996570133259557721408277884273883007604304 86
UVM_INFO @ 62035523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rstmgr_leaf_rst_cnsty 98554531118247672609325283504370402894153220776964959112922685073654133711432 96
UVM_INFO @ 124843562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rstmgr_leaf_rst_cnsty 17098780530148628804562732106812679831979368659189661768264328475542440333315 135
UVM_INFO @ 283655664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---