Simulation Results

Simulation Results: rv_dm/use_dmi_interface

22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.21 %

code
84.59 %

assert
96.82 %

func
98.23 %

block
93.85 %

line
94.43 %

branch
83.33 %

toggle
80.25 %

FSM
80.36 %

Validation stages

V1		98.89%
V2		55.12%
V2S		82.22%
V3		10.00%
unmapped		0.00%

178/180 passed

98.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	44.000s	1506.209us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	50.000s	1304.135us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	51.000s	298.993us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	71.000s	18708.267us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	45.000s	997.135us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	51.000s	10718.363us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	54.000s	9759.419us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	104.000s	31216.979us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	90.000s	89102.421us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	40.000s	504.122us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	40.000s	710.034us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	42.000s	343.481us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	47.000s	179.054us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	44.000s	642.480us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	42.000s	2125.602us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	47.000s	179.807us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	47.000s	353.566us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	40.000s	504.122us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	35.000s	388.898us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	49.000s	261.373us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	42.000s	343.481us	2	2	100.00
rom_read_access				2	2	100.00
	rv_dm_rom_read_access	34.000s	68.931us	2	2	100.00
csr_hw_reset				5	5	100.00
	rv_dm_csr_hw_reset	45.000s	533.997us	5	5	100.00
csr_rw				20	20	100.00
	rv_dm_csr_rw	53.000s	128.339us	20	20	100.00
csr_bit_bash				5	5	100.00
	rv_dm_csr_bit_bash	83.000s	8767.791us	5	5	100.00
csr_aliasing				5	5	100.00
	rv_dm_csr_aliasing	79.000s	7985.953us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rv_dm_csr_mem_rw_with_rand_reset	43.000s	440.113us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rv_dm_csr_aliasing	79.000s	7985.953us	5	5	100.00
	rv_dm_csr_rw	53.000s	128.339us	20	20	100.00
mem_walk				5	5	100.00
	rv_dm_mem_walk	51.000s	155.832us	5	5	100.00
mem_partial_access				5	5	100.00
	rv_dm_mem_partial_access	51.000s	155.831us	5	5	100.00

156/283 passed

55.12 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	44.000s	1506.209us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	44.000s	944.351us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	40.000s	630.724us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	42.000s	140.711us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	47.000s	1232.174us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	63.000s	13716.863us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	45.000s	161.734us	0	20	0.00
bad_sba				1	20	5.00
	rv_dm_bad_sba_tl_access	59.000s	14589.756us	1	20	5.00
sba_autoincrement				6	20	30.00
	rv_dm_autoincr_sba_tl_access	206.000s	67808.152us	6	20	30.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	51.000s	265.292us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	41.000s	1046.594us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	36.000s	549.578us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	41.000s	134.043us	0	5	0.00
tap_ctrl_transitions				11	11	100.00
	rv_dm_tap_fsm	41.000s	9943.551us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	104.000s	4980.051us	10	10	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	32.000s	390.786us	1	1	100.00
stress_all				3	50	6.00
	rv_dm_stress_all	10800.000s	0.000us	3	50	6.00
alert_test				50	50	100.00
	rv_dm_alert_test	49.000s	126.316us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rv_dm_tl_errors	47.000s	510.618us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rv_dm_tl_errors	47.000s	510.618us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rv_dm_csr_aliasing	79.000s	7985.953us	5	5	100.00
	rv_dm_csr_hw_reset	45.000s	533.997us	5	5	100.00
	rv_dm_csr_rw	53.000s	128.339us	20	20	100.00
	rv_dm_same_csr_outstanding	53.000s	1529.960us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rv_dm_csr_aliasing	79.000s	7985.953us	5	5	100.00
	rv_dm_csr_hw_reset	45.000s	533.997us	5	5	100.00
	rv_dm_csr_rw	53.000s	128.339us	20	20	100.00
	rv_dm_same_csr_outstanding	53.000s	1529.960us	20	20	100.00

V2S

37/45 passed

82.22 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				23	25	92.00
	rv_dm_sec_cm	44.000s	613.773us	4	5	80.00
	rv_dm_tl_intg_err	60.000s	11001.727us	19	20	95.00
sec_cm_bus_integrity				19	20	95.00
	rv_dm_tl_intg_err	60.000s	11001.727us	19	20	95.00
sec_cm_lc_hw_debug_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	41.000s	1046.594us	2	2	100.00
	rv_dm_debug_disabled	41.000s	87.635us	2	2	100.00
sec_cm_lc_dft_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	41.000s	1046.594us	2	2	100.00
	rv_dm_debug_disabled	41.000s	87.635us	2	2	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	44.000s	1506.209us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				4	10	40.00
	rv_dm_buffered_enable	47.000s	548.976us	4	10	40.00
sec_cm_sba_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	51.000s	135.366us	4	4	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	51.000s	135.366us	4	4	100.00
sec_cm_exec_ctrl_mubi				4	10	40.00
	rv_dm_buffered_enable	47.000s	548.976us	4	10	40.00

1/10 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	10	10.00
	rv_dm_stress_all_with_rand_reset	84.000s	2943.437us	1	10	10.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	200.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				42 test runs
	rv_dm_sba_tl_access	49370112201653659600137899690632779875865790742239632607094527786109969099008	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24181
	rv_dm_bad_sba_tl_access	34198136264195348913748402719370113277365129673731661529002312227347953914995	93	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24314
	rv_dm_autoincr_sba_tl_access	10895051987889222944521028944865707920627316455501923112537583937075529956751	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24149
	rv_dm_sba_tl_access	26370937865183469300984415657088325918362239461790686854062770632688928586258	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24236
	rv_dm_autoincr_sba_tl_access	22393617306475645202360997546858940015137791207648811874106774483167757850979	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @33519
	rv_dm_sba_tl_access	65378980826058921309901793145817332862497300601246478242253049228356236921635	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24241
	rv_dm_bad_sba_tl_access	89307592853548805788856554036292339437846360410491976862369545724302345270046	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24146
	rv_dm_autoincr_sba_tl_access	84375742289219731851426991762275390121204797184862418644899435416930243741144	150	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24245
	rv_dm_sba_tl_access	5330420733116200909217136311899041007131987504857359595669440487831447643513	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24168
	rv_dm_bad_sba_tl_access	115577398465519720346501857935975981457342181882106341163932327037234487591913	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24236
	rv_dm_autoincr_sba_tl_access	42741979886301858768925040696761442393007386517047169851408833161618069548412	138	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24194
	rv_dm_sba_tl_access	29379731889435906134346911790442015521194869740417665248740135884372390726584	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24208
	rv_dm_bad_sba_tl_access	14818663430148018940790762781889639001038643364139315622761434792571500671084	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24359
	rv_dm_sba_tl_access	103441738979774413529831251721190796778604690968040938284765643710281862772425	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24160
	rv_dm_sba_tl_access	97224833338082650295944211281592232193422242768864268909663959572096760215815	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24108
	rv_dm_bad_sba_tl_access	110594419073379356599121390048030819755833463259778228491690571496535048879274	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24305
	rv_dm_sba_tl_access	19246433630324271878692761993098666834368252556830908996993549744679646486797	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24250
	rv_dm_delayed_resp_sba_tl_access	15334825715178002787148564514712523391531239618193719565643646286905987154571	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24257
	rv_dm_bad_sba_tl_access	39692846792457095183911225202668283516566276607876331335657692899551403448343	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24364
	rv_dm_sba_tl_access	1327661412950241650314704366160285643926237306889841172832221200355936790701	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24186
	rv_dm_sba_tl_access	61109722904069348463347770999130910018209917633089869170121944086834730191794	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24215
	rv_dm_sba_tl_access	81197885745157779590674399094067123926162107287426423275934969139337427495598	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24235
	rv_dm_sba_tl_access	18126849244781550034998990813341196657407894548240917274539952119893488081134	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24168
	rv_dm_delayed_resp_sba_tl_access	61811175382424880675812449240334083456138205360150698071887300205328783473136	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24201
	rv_dm_bad_sba_tl_access	78154807386595539436319388839138829769466245054600076365243312186703200567638	108	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24363
	rv_dm_sba_tl_access	56375863518100381359678235095145554046264519897357009253906914375741774620591	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24225
	rv_dm_delayed_resp_sba_tl_access	88212444853363766936275950079238811143516245702082949874701751345485666221394	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24197
	rv_dm_sba_tl_access	59247625489808885752390170556076308006264411943959153749343965800317172884409	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24164
	rv_dm_bad_sba_tl_access	11006261700776231040860020049797790709105254375606629467153534984873968451170	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24166
	rv_dm_sba_tl_access	51102604273518713978882066403199075605116517655736558819653941067512226391435	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24170
	rv_dm_bad_sba_tl_access	89030707577847044893193574133744799323487460429472435750410640720992867073436	132	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24365
	rv_dm_autoincr_sba_tl_access	87653069113790135643775337512660648202865593756024403657628054492804197775275	141	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24385
	rv_dm_sba_tl_access	21621692338367027659550677599181209040656491369914248392936789904367889257978	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24236
	rv_dm_bad_sba_tl_access	15209971549082818170046262744076490660970368621917141775328825849064598318327	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24145
	rv_dm_sba_tl_access	62322237171170217562818584956769658971325090402916281341182755570564034338702	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24179
	rv_dm_bad_sba_tl_access	78328602837431242199316183941717901582938200708592677772941357527594105334965	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24284
	rv_dm_autoincr_sba_tl_access	83125290145939857163741357858639173006449817785801793552690217715228557436563	147	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24344
	rv_dm_sba_tl_access	87659869336417179505002254540380914623845327973036334430488429858556500206794	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24108
	rv_dm_bad_sba_tl_access	45820217695827007706455103543174531436523341254637814639280674540664132622934	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24223
	rv_dm_sba_tl_access	23483307151561699334821532455242751376960218267401652419025014792313042439419	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24202
	rv_dm_sba_tl_access	1999578175440596033866458677340814237871625992085077249579442710064399003180	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24106
	rv_dm_bad_sba_tl_access	1292183741741812330922043393204061571273347852945866588548732519898127453907	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24183
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				31 test runs
	rv_dm_delayed_resp_sba_tl_access	101421237896838773288797411274371940587089048366825628354377021234033133436603	107	UVM_INFO @ 71119463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	80175055839845046489453117320608061181352106660605579739574613391010494111144	107	UVM_INFO @ 287843145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	72807529524118057996164084471368936888956850691477694405828378187546339259350	107	UVM_INFO @ 260996376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	85485036585338494361204034483091031956858572886994360250554070058097465408179	107	UVM_INFO @ 704159191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	33860446032135303588511203684984432414761390653233023734345472934283472479042	107	UVM_INFO @ 412620319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	10768359677628477404414896632726113137383349246704907965332471784059859324861	107	UVM_INFO @ 59669575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	25956030104015870647590618061420338942217704816304670386246183077117646482801	107	UVM_INFO @ 74445732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	113704765970786539115472694748861638019631823022188714053003539884223704269216	107	UVM_INFO @ 1712288171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	6645976663305977132325542004511692657574672245806642432021783170868004708550	107	UVM_INFO @ 161734003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	27712515914736054811392370302390934551207696586127605889516962553751018536924	107	UVM_INFO @ 1131669306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	27296930660785538008301452162134380923672436752835597378644496153512227028733	107	UVM_INFO @ 302931683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	64987828994240274523650826641281560130832933953159867386983574533696739187200	107	UVM_INFO @ 399707745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	4556286243615238225834393444519805234087259070953660779573245449590385775248	107	UVM_INFO @ 138922875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	102207687380813179265896302420277097605176962127239468697146180177992753680002	107	UVM_INFO @ 234513906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	86340802921169895861749887010524523315882838462572034907921393958447580885317	107	UVM_INFO @ 151395672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	25686786097032132667549768131526745266181247825231464889287098173282043834883	107	UVM_INFO @ 202699645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	70802003932789469197178492600222280813552906921692023979038808371395552248059	107	UVM_INFO @ 121801664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	77645310338187877421970934120844796207227466472320844907597910817432406269625	107	UVM_INFO @ 126397205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	72726413962699670347130702630089752538317273321039301545098801257040540238509	107	UVM_INFO @ 321973093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	53100423263256998903589925570483846390696593419501395292518968870481303782180	107	UVM_INFO @ 151149161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	71400302623362567196812045584733226033774091556111314739961175471334301610169	107	UVM_INFO @ 77894933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	62584834586860641708828007330252071360459347422516494913021974516323700167047	107	UVM_INFO @ 1679874343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	38042820156840090096446616163181010440336084674190834142336304801485743853918	107	UVM_INFO @ 183518831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	114233556051740410104409811488199458808871415570015939379166220415252412079093	107	UVM_INFO @ 133760793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	107918582635848315719644107814415915541377799560834860092414677807161215551674	107	UVM_INFO @ 103303696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	99697212834645653495418171327955969201010479803555978791026914548260762224381	107	UVM_INFO @ 194032543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	75307919813777045810187777540944724046656178756436111750748000964793740863760	107	UVM_INFO @ 66461739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	5780996498880320567367495687232021092013914243565610017969239096051672729571	107	UVM_INFO @ 106399257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	27714206356818356302524656550355380164067370925069856949061656728516696137880	107	UVM_INFO @ 47571993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	9994099043865489750394291604516215999505974507589528826019427381616399624728	107	UVM_INFO @ 73417423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	90698374413459880626176560153862940965528656546980964722583798728970000772251	107	UVM_INFO @ 185221413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				22 test runs
	rv_dm_mem_tl_access_resuming	64203284450570714964727598418025859749971574402539983872484354620464602858942	87	UVM_INFO @ 63148419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	54261280746318842487370848470730459148349394441393492692705783224557716306572	91	UVM_INFO @ 1353239047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	51639765154446536900276417313867579286061209949051639405530759612028099752327	93	UVM_INFO @ 174191850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	94589683896390887291125073507455003724289922630361150370105951155348297515719	87	UVM_INFO @ 179053942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	54470902474772180053892954260133018008586640948260846089137284439486544768060	133	UVM_INFO @ 2203239721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	80674297953614714224160563590128394558103791640426580621980312142267216979902	91	UVM_INFO @ 136761942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	74895769560671741163783021046429519669421914703019499893452468548520794705924	92	UVM_INFO @ 3156807481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	102057809724808496927970141397467597117561026528203470925135213139442481405193	116	UVM_INFO @ 4906614038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	4924663764847237719065928021978736034342056883936653078010989893418631606966	89	UVM_INFO @ 376319687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	21217861755002349645648844858161993895801550086159494557078684315129037912682	92	UVM_INFO @ 5197121683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	45117384880241360062448519827286077150720278049776788578439205382517512995834	89	UVM_INFO @ 850398406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	72936360537469978180889894468587623865071393260449736485942506685032045238760	93	UVM_INFO @ 5831919320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	94611979329919182810918256359073082465392122657071851876723283519569881529755	88	UVM_INFO @ 440459354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	106469408400893529422064836533684826031698492940247797466200952042917839117335	90	UVM_INFO @ 1401996810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	106752941681082372073413153592089585076933991084524973870142958625381985273682	88	UVM_INFO @ 388551266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	38245232758194374426889098980605421852777452638734404329206628174772643757748	88	UVM_INFO @ 173757848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	30529934338286735603727197788751299521045154578192541659615240129843256876810	88	UVM_INFO @ 87818079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	13205544011127608014354285447290935111122111137278970330771577913073417608750	88	UVM_INFO @ 272435097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	98945308746282985355896949059808543633931286230870158046425430777843607596392	88	UVM_INFO @ 536510201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	108854886118116017573941220025934480845666307654745370548610100798072676897473	89	UVM_INFO @ 1426392677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	65759676284360585432086202630941238177176450828662398223316723983245898053961	88	UVM_INFO @ 138191118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	97368264723660000039375026258827119533096662177512941163064799300950810191072	90	UVM_INFO @ 412478581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				17 test runs
	rv_dm_jtag_dmi_debug_disabled	58736826393263494975876428701024846409654106050564792762414444059819846655350	87	UVM_INFO @ 265292423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	19963772243946542002246254298836364346120663958001465038642458979943123787289	87	UVM_INFO @ 169605288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	21643205191663486403358249553002058713433071825976844718665908057731261871610	89	UVM_INFO @ 325093807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	59657494922948172810485354627007651138793864508856849509324453864467937218738	88	UVM_INFO @ 681982911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	40863826928998442657720346779118207500918721036045657212590843488904623776118	91	UVM_INFO @ 578836518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	45612074817358010544200904494048983166132442822360898403486214474590360232526	89	UVM_INFO @ 380446621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	32587363018635240101029997003911745343048863535189754359109883004137083945844	88	UVM_INFO @ 108228742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	57681564549896006057495752789058411400133297520074564194178893241074449515989	92	UVM_INFO @ 1369291711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	14157448947633745786459176725804220448206976965905260011046247988803111614082	88	UVM_INFO @ 745576777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	79501493002213134214960569052927373033059460841630121842721075023184074154252	89	UVM_INFO @ 777339849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	73672043885310432929490140573996737954083372007788602849552256397030051879881	89	UVM_INFO @ 1327212923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	112566523031917806594100486135846604806984872730863909080762022834218456557773	88	UVM_INFO @ 102598760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	27162651661123825254596204099932636133958845503856288655399605462752885768498	90	UVM_INFO @ 1092173436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	19288983610426962105607740720465830014773646134221057325096427615333166208758	90	UVM_INFO @ 935560844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	21953525340121091925276800098355169978602963722343536446565179494633254349889	91	UVM_INFO @ 851777281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	99852051933801192099681803746044062819617231968971545631397883491829107578513	119	UVM_INFO @ 1875408361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	96657187872232826052821478482519801389840366336727021429706581902072623907103	90	UVM_INFO @ 1469378401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				13 test runs
	rv_dm_hart_unavail	95659007358129362441017448356640981556124967099731634820227999285537771966515	87	UVM_INFO @ 51678929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	19412019807408525577793683343818600362175693900565131214861732127467316943630	87	UVM_INFO @ 44959069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	4532226924659918586882939218608518692599211807067414105778539151816250327841	87	UVM_INFO @ 90063307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	25762970327877226033221284380437348639019814165333410126600186114073465011225	87	UVM_INFO @ 232578771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	19676196938652064331608598943427636645106879004170941714386256191248592602654	87	UVM_INFO @ 134042744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	53508809776890978329498004615060699468945610697932408404778172706726384113738	110	UVM_INFO @ 1508356091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	113690412100551054142841497718670041646858246812508904853377259925480620211603	106	UVM_INFO @ 641046078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	63757243692679755478910606801570387228560835991729754350938310726358368986020	89	UVM_INFO @ 372854492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	51571866232193580593980896674629843970805879880922715579244238493361161237260	105	UVM_INFO @ 317686732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	33123943767953270134112753060167014603701638059954537523513498043117498629021	88	UVM_INFO @ 168402947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	103021413710323777486740717843210981837087693005634940201479741894710149619495	88	UVM_INFO @ 387202460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	69360328148472354173418704497088587517763164900105247887507036782684421710816	88	UVM_INFO @ 95153631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	42553101729047964700600178895851075477808445275589022429268099379745403722900	93	UVM_INFO @ 4673746508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				9 test runs
	rv_dm_scanmode	24440393628288344477804885290259929959656628780017574435042956692839204487908	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	65450165316640463239499983485184348199252451005098833914834237951630117856192	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	37730878511132329552623203831795996673063126301766485023931216124271490565725	94	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	106426030713962007775832878355978194989046334650593342089674457578664091401214	92	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	16572488740544672658045036324494767367332216342182685361915594086579898823699	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	22736070002331925777267836534446856250536530642564437931103166040571671005934	92	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	107680284385129119952238753600493299620475940052098918281608562468974459257593	92	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	63217560100583783219367402713721716443448479991822458573815518210339349064212	95	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	64158534016782012131274472693721749619963034712395773182272253773171380558891	89	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])				6 test runs
	rv_dm_buffered_enable	57061712350922060703419090132482572462121495024934205802829605103802861954139	92	UVM_INFO @ 273101246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	106032522567365450037133127260762545445618539254383417355473389768301297638972	91	UVM_INFO @ 169584853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	32288745275205582855929016783738649414175727122676031368352032527281532248983	89	UVM_INFO @ 585084794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	56123586810597278181428714753766274944558264145090385563007084019396900665937	93	UVM_INFO @ 289967676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	110476417159435839726334624325417682497254609565925601156973123836925792822087	90	UVM_INFO @ 641517640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	4608987998650262366297890195694926562959613184847857025276653526010846463048	91	UVM_INFO @ 114184285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				3 test runs
	rv_dm_stress_all	55229060140285936903311180816672743339589094085115390046846541177842959537405	None
	rv_dm_stress_all	65972909776250954567413552963133548810400070163819155703171090004732367714508	None
	rv_dm_stress_all	73845275100583567378700239541227108270911311743193689937570965116909303201541	None
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done)				2 test runs
	rv_dm_stress_all_with_rand_reset	94130049450643379107075019331208073705907837111748429728734129601921022908195	111	UVM_INFO @ 3597454563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	47956004738249237441461036590217684960339974231953353206781095262877729180236	116	UVM_INFO @ 4000874473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1049) virtual_sequencer [rv_dm_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				1 test run
	rv_dm_sec_cm	53238045323205230706047052071936589630024024420703961035105900207266915332014	92	UVM_INFO @ 80319835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [rv_dm_common_vseq] wait timeout occurred!				1 test run
	rv_dm_tl_intg_err	60033288011043493021954104272756045037267216912594971416450124216436319380991	124	UVM_INFO @ 11001727416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---