Simulation Results: rv_timer

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 98.09 %
  • code
  • 95.85 %
  • assert
  • 98.42 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
92.50%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 2.000s 46.452us 20 20 100.00
csr_hw_reset 5 5 100.00
rv_timer_csr_hw_reset 1.000s 47.003us 5 5 100.00
csr_rw 20 20 100.00
rv_timer_csr_rw 2.000s 37.941us 20 20 100.00
csr_bit_bash 5 5 100.00
rv_timer_csr_bit_bash 3.000s 320.004us 5 5 100.00
csr_aliasing 5 5 100.00
rv_timer_csr_aliasing 2.000s 46.109us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 157.401us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rv_timer_csr_rw 2.000s 37.941us 20 20 100.00
rv_timer_csr_aliasing 2.000s 46.109us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 2 20 10.00
rv_timer_random_reset 7.000s 20542.614us 2 20 10.00
disabled 20 20 100.00
rv_timer_disabled 4.000s 2516.271us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 792.000s 3157834.543us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 792.000s 3157834.543us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 8.000s 3147.507us 20 20 100.00
alert_test 50 50 100.00
rv_timer_alert_test 2.000s 39.910us 50 50 100.00
intr_test 50 50 100.00
rv_timer_intr_test 2.000s 16.798us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rv_timer_tl_errors 3.000s 703.115us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rv_timer_tl_errors 3.000s 703.115us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rv_timer_csr_hw_reset 1.000s 47.003us 5 5 100.00
rv_timer_csr_rw 2.000s 37.941us 20 20 100.00
rv_timer_csr_aliasing 2.000s 46.109us 5 5 100.00
rv_timer_same_csr_outstanding 2.000s 41.846us 20 20 100.00
tl_d_partial_access 50 50 100.00
rv_timer_csr_hw_reset 1.000s 47.003us 5 5 100.00
rv_timer_csr_rw 2.000s 37.941us 20 20 100.00
rv_timer_csr_aliasing 2.000s 46.109us 5 5 100.00
rv_timer_same_csr_outstanding 2.000s 41.846us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rv_timer_sec_cm 2.000s 317.167us 5 5 100.00
rv_timer_tl_intg_err 2.000s 387.646us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
rv_timer_tl_intg_err 2.000s 387.646us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 3 10 30.00
rv_timer_min 2.000s 220.243us 3 10 30.00
max_value 0 10 0.00
rv_timer_max 3.000s 932.198us 0 10 0.00
stress_all_with_rand_reset 13 20 65.00
rv_timer_stress_all_with_rand_reset 63.000s 21290.519us 13 20 65.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 25 test runs
rv_timer_random_reset 54472714785091891202886669902775063407225724300365259612818502484914288464968 84
UVM_INFO @ 1145596344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 114858465874125761407961497114024935673842436408466383460901407841207972182212 85
UVM_INFO @ 220243423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 109066105514236257281213539248047665576102517095686634137877896621806107106120 86
UVM_INFO @ 246107119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 32787891817051605549582726347222475224159727002235255167914575635718037777063 85
UVM_INFO @ 183932598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 67564141317989651920088623340002133608689141112545576797519664205151751960253 84
UVM_INFO @ 785567039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 31688457809943839630171851179668564953195020072906864867631342348555000653742 84
UVM_INFO @ 137886339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 91652078149664451787959230008206209979940134751677948019758376234572123172103 86
UVM_INFO @ 59841500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 74783910675555323562980245668643688486924067532375680336515020050291146807180 84
UVM_INFO @ 1375953168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 32070686441960347138192854211652268352314198191439172856901283602351704683032 85
UVM_INFO @ 109217177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 82452753220105930204196389985497198409527213978242876182391400260128340459695 84
UVM_INFO @ 107768916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 36191096204709057141366760516967569240862361665765213514880243099764968812223 87
UVM_INFO @ 67403350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 30525284427480396654888125016417539120965828612095089434317730969697792571221 84
UVM_INFO @ 20542614278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 114514673769707376438344414049650554374685911748674549890519169378121402239414 84
UVM_INFO @ 142074514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 103187904528803954301227346988339421253570199588187387230685263495605970203662 84
UVM_INFO @ 229655385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 34493631926782835270642916710502519276506564641975071592306062477784492940086 84
UVM_INFO @ 619751677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 75085924505449073281439777517828900192088728946244774499324918695751422908485 84
UVM_INFO @ 363886036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 31100781713713948350778859952895297830993750472532992338841710870013227762402 84
UVM_INFO @ 116877443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 108783150929305694109173682687091411462703691644275370583827025366412735473132 84
UVM_INFO @ 332586349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 28290722008318376956993922889386531701327569879772058349552290591497452717877 84
UVM_INFO @ 125201729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 93130555620004515889462401231857760835572639430748084251678470244085482789200 84
UVM_INFO @ 63738749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 112478512997261639123523915375554650530988271818218880862128810030816768595658 84
UVM_INFO @ 4880217685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 43676420615807481337439418582732537283123379276840842766422214788417629790927 84
UVM_INFO @ 101351606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 22508320573919060514206595479456980036651051210849466568418127407508139523894 84
UVM_INFO @ 320034838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 55070496290152536501981406455653435374564812522673707054960551327953435719798 85
UVM_INFO @ 92057143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 56353489466933544738212157993001674730520683972117961088609537117814604379060 84
UVM_INFO @ 295812216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 74717016137899593961123590632842018719334748287395594902565745238288822420866 85
UVM_INFO @ 932198021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 40239135974328191453206474569979955357096991961057541224358222607155389811436 84
UVM_INFO @ 225068197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 109980558983556640508555954308107774125486333788261946829479823499744085248355 84
UVM_INFO @ 154533609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 37376900679555933765854855938887781337683496957415665941580578800374685338938 84
UVM_INFO @ 90196576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 78818354254925197760758669493939073873018723057541124208697352930021724175821 84
UVM_INFO @ 766280985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 111672334164846500219626377871421318170909919012741660645433931788035410785467 84
UVM_INFO @ 42913499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 66401132129930679047710503482209582202689250488473551305885341092668390327443 84
UVM_INFO @ 286776822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 6930197363847963114085100850552566210614398746497501093285199545943178701371 84
UVM_INFO @ 193982242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 66138202189360279651905429341090598834322757286307759034894986007367004291412 84
UVM_INFO @ 192008727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 5 test runs
rv_timer_stress_all_with_rand_reset 9088172454158454904948665736202185166582094312394807034901085166923680632420 88
UVM_INFO @ 22098528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 21396120818175931327401455648898966183282860107631819925073268645479566386260 128
UVM_INFO @ 581309001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 9028901931164039424973336951698681305558576187491295307236449524160666079250 393
UVM_INFO @ 4341925318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 112475472450705514456100973146084116055904858449928456118541493737100426232922 128
UVM_INFO @ 3767954385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 81404160162765692848019071248566058465014325529995259952789792433445599684591 503
UVM_INFO @ 4379417241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
rv_timer_stress_all_with_rand_reset 45168596994855956781200113814668172949839690431720058422844665730011581625315 145
UVM_INFO @ 482298654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 110482677667732689267146901122970705132667837300043866276291822414424437580399 302
UVM_INFO @ 4086772501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:347) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 49109586937104063608328822346906370010790981362679279872706175187783823794033 84
UVM_INFO @ 42472063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---