Simulation Results

Simulation Results: spi_host

22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.19 %

code
95.03 %

assert
96.78 %

func
90.76 %

block
96.96 %

line
98.76 %

branch
93.35 %

toggle
88.02 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		99.48%
V2S		100.00%
unmapped		100.00%

115/115 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	spi_host_smoke	102.000s	10567.889us	50	50	100.00
csr_hw_reset				5	5	100.00
	spi_host_csr_hw_reset	2.000s	19.826us	5	5	100.00
csr_rw				20	20	100.00
	spi_host_csr_rw	2.000s	23.938us	20	20	100.00
csr_bit_bash				5	5	100.00
	spi_host_csr_bit_bash	5.000s	540.366us	5	5	100.00
csr_aliasing				5	5	100.00
	spi_host_csr_aliasing	2.000s	24.107us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	spi_host_csr_mem_rw_with_rand_reset	2.000s	38.496us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	spi_host_csr_rw	2.000s	23.938us	20	20	100.00
	spi_host_csr_aliasing	2.000s	24.107us	5	5	100.00
mem_walk				5	5	100.00
	spi_host_mem_walk	1.000s	36.138us	5	5	100.00
mem_partial_access				5	5	100.00
	spi_host_mem_partial_access	2.000s	35.543us	5	5	100.00

766/770 passed

99.48 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
performance				50	50	100.00
	spi_host_performance	2.000s	28.166us	50	50	100.00
error_event_intr				150	150	100.00
	spi_host_overflow_underflow	31.000s	1500.933us	50	50	100.00
	spi_host_error_cmd	3.000s	39.853us	50	50	100.00
	spi_host_event	194.000s	252247.882us	50	50	100.00
clock_rate				50	50	100.00
	spi_host_speed	8.000s	509.867us	50	50	100.00
speed				50	50	100.00
	spi_host_speed	8.000s	509.867us	50	50	100.00
chip_select_timing				50	50	100.00
	spi_host_speed	8.000s	509.867us	50	50	100.00
sw_reset				49	50	98.00
	spi_host_sw_reset	119.000s	10054.885us	49	50	98.00
passthrough_mode				50	50	100.00
	spi_host_passthrough_mode	2.000s	77.751us	50	50	100.00
cpol_cpha				50	50	100.00
	spi_host_speed	8.000s	509.867us	50	50	100.00
full_cycle				50	50	100.00
	spi_host_speed	8.000s	509.867us	50	50	100.00
duplex				50	50	100.00
	spi_host_smoke	102.000s	10567.889us	50	50	100.00
tx_rx_only				50	50	100.00
	spi_host_smoke	102.000s	10567.889us	50	50	100.00
stress_all				49	50	98.00
	spi_host_stress_all	417.000s	1000000.000us	49	50	98.00
spien				50	50	100.00
	spi_host_spien	243.000s	7191.956us	50	50	100.00
stall				48	50	96.00
	spi_host_status_stall	1526.000s	520100.059us	48	50	96.00
Idlecsbactive				50	50	100.00
	spi_host_idlecsbactive	31.000s	3171.633us	50	50	100.00
data_fifo_status				50	50	100.00
	spi_host_overflow_underflow	31.000s	1500.933us	50	50	100.00
alert_test				50	50	100.00
	spi_host_alert_test	2.000s	49.094us	50	50	100.00
intr_test				50	50	100.00
	spi_host_intr_test	2.000s	21.362us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	spi_host_tl_errors	4.000s	217.137us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	spi_host_tl_errors	4.000s	217.137us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	spi_host_csr_hw_reset	2.000s	19.826us	5	5	100.00
	spi_host_csr_rw	2.000s	23.938us	20	20	100.00
	spi_host_csr_aliasing	2.000s	24.107us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	50.338us	20	20	100.00
tl_d_partial_access				50	50	100.00
	spi_host_csr_hw_reset	2.000s	19.826us	5	5	100.00
	spi_host_csr_rw	2.000s	23.938us	20	20	100.00
	spi_host_csr_aliasing	2.000s	24.107us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	50.338us	20	20	100.00

V2S

25/25 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	spi_host_tl_intg_err	3.000s	113.306us	20	20	100.00
	spi_host_sec_cm	2.000s	76.319us	5	5	100.00
sec_cm_bus_integrity				20	20	100.00
	spi_host_tl_intg_err	3.000s	113.306us	20	20	100.00

unmapped

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				10	10	100.00
	spi_host_upper_range_clkdiv	774.000s	44004.717us	10	10	100.00

Error Messages

	Test	seed	line	log context
xmsim: E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed				2 test runs
	spi_host_status_stall	61068455883345333079124269607579344727466909069823272589775158020330454524054	2125	UVM_ERROR @ 439853161 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=439853000 ps UVM_INFO @ 439853161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	spi_host_status_stall	65855504644721002445962314834852729655846403812239704939682650330383156174735	1490	UVM_ERROR @ 5252086731 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=5252087000 ps UVM_INFO @ 5252086731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	spi_host_stress_all	17125048359901053504049206626394254229785534695450513434843783648298220607702	314	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = ns spi_host_reg_block.status.rxempty (addr=, Comparison=CompareOpEq, exp_data=, call_count=				1 test run
	spi_host_sw_reset	37692307537055201742974194227344822454136068068100768652070776494884073658472	429	UVM_INFO @ 10054885007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---