Simulation Results: sram_ctrl/main

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.22 %
  • code
  • 96.96 %
  • assert
  • 98.09 %
  • func
  • 96.60 %
  • block
  • 96.35 %
  • line
  • 97.11 %
  • branch
  • 94.65 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 9.000s 4117.639us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 2.000s 47.822us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 169.416us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 4.000s 207.732us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 19.696us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 1493.356us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 169.416us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 19.696us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 185.000s 15163.264us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 129.000s 9685.805us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 48.000s 9425.695us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 187.000s 3892.723us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 185.000s 55559.695us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 100.000s 70827.177us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 60.000s 15844.296us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 38.000s 5553.722us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 8.000s 2561.186us 5 5 100.00
sram_ctrl_partial_access_b2b 302.000s 42397.323us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 8.000s 1355.375us 5 5 100.00
sram_ctrl_throughput_w_partial_write 8.000s 2759.687us 5 5 100.00
sram_ctrl_throughput_w_readback 7.000s 2654.069us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 16.000s 1911.690us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 4.000s 351.114us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 434.000s 51881.683us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 39.377us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.000s 164.323us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.000s 164.323us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 47.822us 5 5 100.00
sram_ctrl_csr_rw 2.000s 169.416us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 19.696us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 24.177us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 47.822us 5 5 100.00
sram_ctrl_csr_rw 2.000s 169.416us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 19.696us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 24.177us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 41.000s 26420.722us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_sec_cm 6.000s 1105.902us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 491.278us 20 20 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 6.000s 1105.902us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.000s 491.278us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 16.000s 1911.690us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 16.000s 1911.690us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 169.416us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 38.000s 5553.722us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 38.000s 5553.722us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 38.000s 5553.722us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 60.000s 15844.296us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 8.000s 2799.608us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 41.000s 26420.722us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 7.000s 702.038us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 9.000s 4117.639us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 9.000s 4117.639us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 38.000s 5553.722us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 6.000s 1105.902us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 60.000s 15844.296us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 6.000s 1105.902us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 1105.902us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 9.000s 4117.639us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 1105.902us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 61.000s 1850.763us 5 5 100.00