Simulation Results: sram_ctrl/ret

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.67 %
  • code
  • 83.34 %
  • assert
  • 98.08 %
  • func
  • 96.60 %
  • block
  • 93.73 %
  • line
  • 94.89 %
  • branch
  • 89.51 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 3.000s 228.491us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.000s 48.917us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 44.140us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 4.000s 179.985us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 41.694us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 448.369us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 44.140us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 41.694us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 12.000s 775.276us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 6.000s 172.477us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 15.000s 3367.162us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 188.000s 4529.776us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 7.000s 239.096us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 23.000s 2540.809us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 7.000s 463.128us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 20.000s 1274.830us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 2.000s 135.946us 5 5 100.00
sram_ctrl_partial_access_b2b 328.000s 43135.305us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 2.000s 66.937us 5 5 100.00
sram_ctrl_throughput_w_partial_write 2.000s 53.192us 5 5 100.00
sram_ctrl_throughput_w_readback 2.000s 43.860us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 10.000s 168.112us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 2.000s 49.054us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 57.000s 3647.081us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 13.807us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 7.000s 307.212us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 7.000s 307.212us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.000s 48.917us 5 5 100.00
sram_ctrl_csr_rw 2.000s 44.140us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 41.694us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 20.722us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.000s 48.917us 5 5 100.00
sram_ctrl_csr_rw 2.000s 44.140us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 41.694us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 20.722us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 1787.881us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_sec_cm 5.000s 1521.968us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 215.704us 20 20 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 1521.968us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.000s 215.704us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 10.000s 168.112us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 10.000s 168.112us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 44.140us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 20.000s 1274.830us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 20.000s 1274.830us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 20.000s 1274.830us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 7.000s 463.128us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 2.000s 34.568us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 1787.881us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 2.000s 39.954us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 3.000s 228.491us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 3.000s 228.491us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 20.000s 1274.830us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 1521.968us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 7.000s 463.128us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 1521.968us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1521.968us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 3.000s 228.491us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1521.968us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 113.000s 2226.579us 5 5 100.00