Simulation Results: ac_range_check

 
30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.30 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.63 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
98.11%
V2
97.73%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 20 20 100.00
ac_range_check_smoke 52.000s 1526.141us 20 20 100.00
ac_range_check_smoke_racl 19 20 95.00
ac_range_check_smoke_racl 74.000s 2488.681us 19 20 95.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 3.000s 42.565us 1 1 100.00
csr_rw 5 5 100.00
ac_range_check_csr_rw 3.000s 231.691us 5 5 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 34.000s 477.644us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 27.000s 1176.584us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 28.276us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
ac_range_check_csr_rw 3.000s 231.691us 5 5 100.00
ac_range_check_csr_aliasing 27.000s 1176.584us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 62.893us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 50.000s 20914.805us 1 1 100.00
stress_all 8 10 80.00
ac_range_check_stress_all 263.000s 44385.030us 8 10 80.00
alert_test 10 10 100.00
ac_range_check_alert_test 23.000s 42.119us 10 10 100.00
intr_test 10 10 100.00
ac_range_check_intr_test 2.000s 25.954us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
ac_range_check_tl_errors 6.000s 154.578us 25 25 100.00
tl_d_illegal_access 25 25 100.00
ac_range_check_tl_errors 6.000s 154.578us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
ac_range_check_csr_hw_reset 3.000s 42.565us 1 1 100.00
ac_range_check_csr_rw 3.000s 231.691us 5 5 100.00
ac_range_check_csr_aliasing 27.000s 1176.584us 1 1 100.00
ac_range_check_same_csr_outstanding 7.000s 159.019us 5 5 100.00
tl_d_partial_access 12 12 100.00
ac_range_check_csr_hw_reset 3.000s 42.565us 1 1 100.00
ac_range_check_csr_rw 3.000s 231.691us 5 5 100.00
ac_range_check_csr_aliasing 27.000s 1176.584us 1 1 100.00
ac_range_check_same_csr_outstanding 7.000s 159.019us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 24.000s 1084.174us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 24.000s 1084.174us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 24.000s 1084.174us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 24.000s 1084.174us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 128.000s 19905.515us 20 20 100.00
tl_intg_err 30 30 100.00
ac_range_check_sec_cm 2.000s 12.440us 5 5 100.00
ac_range_check_tl_intg_err 14.000s 420.107us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
ac_range_check_stress_all_with_rand_reset 376.000s 7905.625us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 50.000s 1589.929us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 3 test runs
ac_range_check_stress_all 68270021636025163509367327661160034219726527768375663487161483669858438550668 12859
UVM_INFO @ 23193600912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 97572711549600260417834159475869090591939294254478514730614178088449017915220 4083
UVM_INFO @ 14724826727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 75833671992927975845583177573441312853059286699644569257572003082703143679206 4418
UVM_INFO @ 8370201459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---