Simulation Results

Simulation Results: aes/gcm_masked

30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
97.34 %

code
98.07 %

assert
98.57 %

func
95.37 %

block
98.13 %

line
99.24 %

branch
94.98 %

toggle
98.05 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		99.06%
V2S		94.62%
V3		0.00%

24/24 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wake_up				1	1	100.00
	aes_wake_up	3.000s	65.481us	1	1	100.00
smoke				10	10	100.00
	aes_smoke	4.000s	266.136us	10	10	100.00
csr_hw_reset				1	1	100.00
	aes_csr_hw_reset	1.000s	57.900us	1	1	100.00
csr_rw				5	5	100.00
	aes_csr_rw	2.000s	56.361us	5	5	100.00
csr_bit_bash				1	1	100.00
	aes_csr_bit_bash	12.000s	2418.679us	1	1	100.00
csr_aliasing				1	1	100.00
	aes_csr_aliasing	3.000s	275.375us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	aes_csr_mem_rw_with_rand_reset	2.000s	135.451us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	aes_csr_rw	2.000s	56.361us	5	5	100.00
	aes_csr_aliasing	3.000s	275.375us	1	1	100.00

316/319 passed

99.06 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
algorithm				70	70	100.00
	aes_smoke	4.000s	266.136us	10	10	100.00
	aes_config_error	58.000s	2768.973us	50	50	100.00
	aes_stress	10.000s	261.637us	10	10	100.00
key_length				70	70	100.00
	aes_smoke	4.000s	266.136us	10	10	100.00
	aes_config_error	58.000s	2768.973us	50	50	100.00
	aes_stress	10.000s	261.637us	10	10	100.00
back2back				35	35	100.00
	aes_stress	10.000s	261.637us	10	10	100.00
	aes_b2b	29.000s	898.194us	25	25	100.00
backpressure				10	10	100.00
	aes_stress	10.000s	261.637us	10	10	100.00
multi_message				93	95	97.89
	aes_smoke	4.000s	266.136us	10	10	100.00
	aes_config_error	58.000s	2768.973us	50	50	100.00
	aes_stress	10.000s	261.637us	10	10	100.00
	aes_alert_reset	12.000s	1573.778us	23	25	92.00
failure_test				83	85	97.65
	aes_man_cfg_err	4.000s	155.884us	10	10	100.00
	aes_config_error	58.000s	2768.973us	50	50	100.00
	aes_alert_reset	12.000s	1573.778us	23	25	92.00
trigger_clear_test				10	10	100.00
	aes_clear	12.000s	1356.296us	10	10	100.00
nist_test_vectors				1	1	100.00
	aes_nist_vectors	75.000s	5198.284us	1	1	100.00
nist_test_vectors_gcm				1	1	100.00
	aes_nist_vectors_gcm	11.000s	1163.068us	1	1	100.00
reset_recovery				23	25	92.00
	aes_alert_reset	12.000s	1573.778us	23	25	92.00
stress				10	10	100.00
	aes_stress	10.000s	261.637us	10	10	100.00
sideload				20	20	100.00
	aes_stress	10.000s	261.637us	10	10	100.00
	aes_sideload	7.000s	839.725us	10	10	100.00
deinitialization				10	10	100.00
	aes_deinit	5.000s	504.622us	10	10	100.00
stress_all				9	10	90.00
	aes_stress_all	75.000s	31523.671us	9	10	90.00
gcm_save_and_restore				100	100	100.00
	aes_gcm_save_restore	20.000s	2913.961us	100	100	100.00
alert_test				10	10	100.00
	aes_alert_test	3.000s	52.203us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	aes_tl_errors	3.000s	159.038us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	aes_tl_errors	3.000s	159.038us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	aes_csr_hw_reset	1.000s	57.900us	1	1	100.00
	aes_csr_rw	2.000s	56.361us	5	5	100.00
	aes_csr_aliasing	3.000s	275.375us	1	1	100.00
	aes_same_csr_outstanding	3.000s	112.114us	5	5	100.00
tl_d_partial_access				12	12	100.00
	aes_csr_hw_reset	1.000s	57.900us	1	1	100.00
	aes_csr_rw	2.000s	56.361us	5	5	100.00
	aes_csr_aliasing	3.000s	275.375us	1	1	100.00
	aes_same_csr_outstanding	3.000s	112.114us	5	5	100.00

V2S

1107/1170 passed

94.62 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reseeding				10	10	100.00
	aes_reseed	8.000s	205.740us	10	10	100.00
fault_inject				608	660	92.12
	aes_fi	7.000s	135.150us	10	10	100.00
	aes_control_fi	62.042s	0.000us	276	300	92.00
	aes_cipher_fi	61.000s	0.000us	322	350	92.00
shadow_reg_update_error				20	20	100.00
	aes_shadow_reg_errors	4.000s	1071.719us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	aes_shadow_reg_errors	4.000s	1071.719us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	aes_shadow_reg_errors	4.000s	1071.719us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	aes_shadow_reg_errors	4.000s	1071.719us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	aes_shadow_reg_errors_with_csr_rw	6.000s	361.182us	20	20	100.00
tl_intg_err				30	30	100.00
	aes_sec_cm	11.000s	1720.587us	5	5	100.00
	aes_tl_intg_err	5.000s	693.985us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	aes_tl_intg_err	5.000s	693.985us	25	25	100.00
sec_cm_lc_escalate_en_intersig_mubi				23	25	92.00
	aes_alert_reset	12.000s	1573.778us	23	25	92.00
sec_cm_main_config_shadow				20	20	100.00
	aes_shadow_reg_errors	4.000s	1071.719us	20	20	100.00
sec_cm_gcm_config_shadow				20	20	100.00
	aes_shadow_reg_errors	4.000s	1071.719us	20	20	100.00
sec_cm_main_config_sparse				134	145	92.41
	aes_smoke	4.000s	266.136us	10	10	100.00
	aes_stress	10.000s	261.637us	10	10	100.00
	aes_alert_reset	12.000s	1573.778us	23	25	92.00
	aes_core_fi	330.000s	10016.512us	91	100	91.00
sec_cm_gcm_config_sparse				251	260	96.54
	aes_gcm_save_restore	20.000s	2913.961us	100	100	100.00
	aes_config_error	58.000s	2768.973us	50	50	100.00
	aes_stress	10.000s	261.637us	10	10	100.00
	aes_core_fi	330.000s	10016.512us	91	100	91.00
sec_cm_aux_config_shadow				20	20	100.00
	aes_shadow_reg_errors	4.000s	1071.719us	20	20	100.00
sec_cm_aux_config_regwen				20	20	100.00
	aes_readability	3.000s	100.131us	10	10	100.00
	aes_stress	10.000s	261.637us	10	10	100.00
sec_cm_key_sideload				20	20	100.00
	aes_stress	10.000s	261.637us	10	10	100.00
	aes_sideload	7.000s	839.725us	10	10	100.00
sec_cm_key_sw_unreadable				10	10	100.00
	aes_readability	3.000s	100.131us	10	10	100.00
sec_cm_data_reg_sw_unreadable				10	10	100.00
	aes_readability	3.000s	100.131us	10	10	100.00
sec_cm_key_sec_wipe				10	10	100.00
	aes_readability	3.000s	100.131us	10	10	100.00
sec_cm_iv_config_sec_wipe				10	10	100.00
	aes_readability	3.000s	100.131us	10	10	100.00
sec_cm_data_reg_sec_wipe				10	10	100.00
	aes_readability	3.000s	100.131us	10	10	100.00
sec_cm_data_reg_key_sca				10	10	100.00
	aes_stress	10.000s	261.637us	10	10	100.00
sec_cm_key_masking				10	10	100.00
	aes_stress	10.000s	261.637us	10	10	100.00
sec_cm_main_fsm_sparse				10	10	100.00
	aes_fi	7.000s	135.150us	10	10	100.00
sec_cm_main_fsm_redun				633	685	92.41
	aes_fi	7.000s	135.150us	10	10	100.00
	aes_control_fi	62.042s	0.000us	276	300	92.00
	aes_cipher_fi	61.000s	0.000us	322	350	92.00
	aes_ctr_fi	7.000s	49.801us	25	25	100.00
sec_cm_cipher_fsm_sparse				10	10	100.00
	aes_fi	7.000s	135.150us	10	10	100.00
sec_cm_cipher_fsm_redun				608	660	92.12
	aes_fi	7.000s	135.150us	10	10	100.00
	aes_control_fi	62.042s	0.000us	276	300	92.00
	aes_cipher_fi	61.000s	0.000us	322	350	92.00
sec_cm_cipher_ctr_redun				322	350	92.00
	aes_cipher_fi	61.000s	0.000us	322	350	92.00
sec_cm_ctr_fsm_sparse				10	10	100.00
	aes_fi	7.000s	135.150us	10	10	100.00
sec_cm_ctr_fsm_redun				311	335	92.84
	aes_fi	7.000s	135.150us	10	10	100.00
	aes_control_fi	62.042s	0.000us	276	300	92.00
	aes_ctr_fi	7.000s	49.801us	25	25	100.00
sec_cm_ghash_fsm_sparse				10	10	100.00
	aes_fi	7.000s	135.150us	10	10	100.00
sec_cm_ctrl_sparse				633	685	92.41
	aes_fi	7.000s	135.150us	10	10	100.00
	aes_control_fi	62.042s	0.000us	276	300	92.00
	aes_cipher_fi	61.000s	0.000us	322	350	92.00
	aes_ctr_fi	7.000s	49.801us	25	25	100.00
sec_cm_main_fsm_global_esc				23	25	92.00
	aes_alert_reset	12.000s	1573.778us	23	25	92.00
sec_cm_main_fsm_local_esc				633	685	92.41
	aes_fi	7.000s	135.150us	10	10	100.00
	aes_control_fi	62.042s	0.000us	276	300	92.00
	aes_cipher_fi	61.000s	0.000us	322	350	92.00
	aes_ctr_fi	7.000s	49.801us	25	25	100.00
sec_cm_cipher_fsm_local_esc				633	685	92.41
	aes_fi	7.000s	135.150us	10	10	100.00
	aes_control_fi	62.042s	0.000us	276	300	92.00
	aes_cipher_fi	61.000s	0.000us	322	350	92.00
	aes_ctr_fi	7.000s	49.801us	25	25	100.00
sec_cm_ctr_fsm_local_esc				311	335	92.84
	aes_fi	7.000s	135.150us	10	10	100.00
	aes_control_fi	62.042s	0.000us	276	300	92.00
	aes_ctr_fi	7.000s	49.801us	25	25	100.00
sec_cm_ghash_fsm_local_esc				100	100	100.00
	aes_ghash_fi	9.000s	567.081us	90	90	100.00
	aes_fi	7.000s	135.150us	10	10	100.00
sec_cm_data_reg_local_esc				608	660	92.12
	aes_fi	7.000s	135.150us	10	10	100.00
	aes_control_fi	62.042s	0.000us	276	300	92.00
	aes_cipher_fi	61.000s	0.000us	322	350	92.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	aes_stress_all_with_rand_reset	32.000s	1008.814us	0	10	0.00

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				24 test runs
	aes_control_fi	110041153048687428568435265321923592424609617681292380138325189900305943663947	None
	aes_control_fi	4434987637944669237770437910342939452799092758318407910327793765285530785925	None
	aes_cipher_fi	15462931828621748970127701957706227832822221333244066452726741738462936306898	None
	aes_control_fi	30893437987622916559246575267510646782799914164764255047901449664868251520709	None
	aes_control_fi	81155647254623462853021420133486130336113056313522987479722658066123477967331	None
	aes_control_fi	99082918937665007438450271473650909001858601998396976053292077610932158784133	None
	aes_control_fi	29819539351384987808609826684508593846043208723734358343689597509433796134412	None
	aes_control_fi	81331538764173661746335947088190501081268191326244023838948003716835373106116	None
	aes_cipher_fi	43279984979132228487813188267762917778599552998782609899287811707988634870331	None
	aes_cipher_fi	97522161689457799586563131180531104917408398092613779321574537529269759373901	None
	aes_control_fi	98701034057493268556575973697343312365177318707705671656981778458530278384829	None
	aes_control_fi	67088950242952280042729020782456559396254606667894311415189945219024685085836	None
	aes_cipher_fi	29569397181656589324364339365949541231392228927745149658851587601385863417523	None
	aes_control_fi	101103590005360323405617913544750348496266460411997648789491664975000034084201	None
	aes_cipher_fi	87126531675462069499087216591892680286739488573048778247955620955340044513156	None
	aes_cipher_fi	77864457657221367494326120794032345491324308287261566912634393977423849745019	None
	aes_control_fi	7140728552328056677913476949956473738877128407105061998752611367517307732874	None
	aes_control_fi	114791911845602963715121527239530068747113927943997197463738168480352075994645	None
	aes_control_fi	24481821278544258262001328785909836450990616182562930975800125309715919621813	None
	aes_control_fi	93682617007869007307687382505521836656091196333655949564686524810703187408012	None
	aes_cipher_fi	63350846540468960033326842093950404761545406504796718455731910523409644907968	None
	aes_cipher_fi	111118362310593609362596881111942429343157417148578376922377885540651796547662	None
	aes_cipher_fi	80610363765158296260803399439864170008488955644984107880613923683088686731535	None
	aes_cipher_fi	70431738372593595369608813814999485274793851994439166621146905361575214056276	None
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!				18 test runs
	aes_cipher_fi	335072434562387233107389379463325817372976231674006481745438966943526330700	157	UVM_INFO @ 10008299836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	83495014453390234367357699114430615324845958083102745962715161282914956858860	154	UVM_INFO @ 10017463294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	15747982617767747093431144485357380205948238549125888842530626216251573124269	156	UVM_INFO @ 10023814759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	89827959153744940964941028032651462152442070684459719450674124457881745781266	146	UVM_INFO @ 10030109526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	91153477946547800919018914567337023443034346428077566296807679534840080278942	155	UVM_INFO @ 10014370923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	78534654648481536930109175513788926349543840053323604824226644576288671495609	154	UVM_INFO @ 10409443348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	47721157551162158356569556012066493042912882912497782056392930207035375140532	154	UVM_INFO @ 10059788405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	29376262447991699041253401918467224997178295095744563085299478687164822539686	144	UVM_INFO @ 10010508955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	37812500688186620152066378598085814453081671910730165433313835079683373003299	152	UVM_INFO @ 10023630701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	13730310468988874280072814759376648125511628889048905223482005047223260716025	156	UVM_INFO @ 10032509857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	98940369341073720512556078238320733737807192650100317058276672003728440067361	154	UVM_INFO @ 10023700732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	64870891949729557881831786656578585749326580136580621142909656781616906254636	154	UVM_INFO @ 10022104900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	95355698052321675521930535932650749517379949821684231810688895443908690631071	146	UVM_INFO @ 10026031269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	8129095834089994195262750977103002866483809414874128694673729224649921788662	146	UVM_INFO @ 10020178569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	89926664726115280695438707250404544946257077403157050102148223586657954381332	144	UVM_INFO @ 10010015686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	23775713420090870090287788088844089121530253911171938152256323863083736844264	148	UVM_INFO @ 10009192182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	51845082944037773376465416465656302230444972718886788522271496273781467969151	146	UVM_INFO @ 10016895427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	72081150399527042839985024263831011111110795667122061083968748740009382534276	150	UVM_INFO @ 10009017871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!				10 test runs
	aes_control_fi	79744154470182901430605008689789981835522688709281586943870486848165483417765	145	UVM_INFO @ 10006852066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	111807140446212503509415829486709319459924808603379715877476983734298922657907	150	UVM_INFO @ 10070410760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	53870391423046151122226762467881338357691605662306440217647456423151201205105	143	UVM_INFO @ 10026687632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	67695477117982720850697010632131217556768463812039206041579756794391753505174	151	UVM_INFO @ 10006438299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	43522798952790817758165233410514544485307758763692157836393609616090794356005	147	UVM_INFO @ 10017078668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	62638045429341245729005639432383827850445636439470540205838488891080648509587	148	UVM_INFO @ 10011628448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	75571619918702066406548155594780049475722167555932374389503230334079087939658	153	UVM_INFO @ 10012058495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	18037104846011164750615345748101250245248647880732369496182436533025798284415	150	UVM_INFO @ 10010312456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	35502120186922688509824717929413218869036666408514714654651092289762363401765	148	UVM_INFO @ 10007253631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	39076511281342684857838213170545492732925273607522817826961883039701282549094	142	UVM_INFO @ 10020471178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred!				7 test runs
	aes_core_fi	87411654655448328862129427808090153837239730397440446272494216584787620008447	147	UVM_INFO @ 10006428900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	7662366812935698059511869519562008159657324071433201467389708512532568292358	149	UVM_INFO @ 10009089292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	19831255490424457600280780069779570714421616080151429868091661699760781182460	152	UVM_INFO @ 10018338495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	103408694767214016198719075111843039243544485289442968118067131813187870834196	147	UVM_INFO @ 10010383756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	102898272879994528745994527434503869738363818427603196150921507878551001638377	154	UVM_INFO @ 10017415434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	25990509806126168775617788261605243907726760845599610035748977510610649418716	151	UVM_INFO @ 10007172917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	62048523615389933238619311977068389534491356278827279498287649436690699893557	148	UVM_INFO @ 10011736264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done)				5 test runs
	aes_stress_all_with_rand_reset	109113083391536792733999794714192183993787064675348087868021623416266036523493	965	UVM_INFO @ 1008814386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	108769948512208425279313427268100966360986481603694922226520255163367032293821	138	UVM_INFO @ 20577767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	90147888385670983586341185458082108544531810538570557843992516157722984302976	145	UVM_INFO @ 27962281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	85897959150701055407072952134257019029459740673899140904527612250853341601495	287	UVM_INFO @ 1789493972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	67677193630078844336976883012470417746795305862771844721931646432635588482424	169	UVM_INFO @ 12263462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)				3 test runs
	aes_stress_all_with_rand_reset	92658358434977134809416497105952499789288706438761602268843785508857461385226	112	UVM_INFO @ 11771530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	43661183568230136116593017360106297800330531453516243958990987969822743639641	112	UVM_INFO @ 11398325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	10955745162736147400527424686451335231694957187431799678282524641705111382039	112	UVM_INFO @ 10419335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error				2 test runs
	aes_alert_reset	109172463495438512699354934766767324398547424898705984949590308360552727937042	27485	UVM_INFO @ 1573778481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_alert_reset	7470598539407141206789947378914233233916249770352540816884278308301458689893	696	UVM_INFO @ 33552698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_/rtl/aes_core.sv,1112): Assertion AesModeValid has failed				1 test run
	aes_stress_all	36533700319686411573173615172019913047741177582713102950425736053520552486956	13215	xmsim: E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 337685683 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed xmsim: E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 337685683 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 337685683 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed UVM_ERROR @ 337685683 ps: (aes_core.sv:1112) [ASSERT FAILED] AesModeValid
UVM_FATAL (aes_base_vseq.sv:311) virtual_sequencer [aes_stress_vseq] Expected GCM phase GCM_TEXT, got GCM_TAG				1 test run
	aes_stress_all_with_rand_reset	82277546954973447229505090257257111967591727703527866161564707012628810657812	450	UVM_INFO @ 333866118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:1031) virtual_sequencer [aes_stress_vseq]				1 test run
	aes_stress_all_with_rand_reset	5811788070635729017193408314489359449664180045981356433044257753232631303031	162	Was able to clear FATAL ALERT without reset ---\| Idle: 0 ---\| Stall: 0
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=, Comparison=CompareOpEq, exp_data=, call_count=8)				1 test run
	aes_core_fi	72037204403886842561859005042131706124541469288279591988614303163324751341591	142	UVM_INFO @ 10016512124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:93) [aes_core_fi_vseq] wait timeout occurred!				1 test run
	aes_core_fi	62195117654173313485691880516328628541697326322268883581263051582117448527897	141	UVM_INFO @ 10198257991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---