| V1 |
|
100.00% |
| V2 |
|
87.97% |
| V2S |
|
97.07% |
| V3 |
|
60.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 69.220s | 1759.461us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 8.740s | 126.532us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 12.350s | 130.742us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 207.850s | 7391.157us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 60.810s | 1249.235us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 17.300s | 743.226us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 12.350s | 130.742us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 60.810s | 1249.235us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 474.060s | 31716.450us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 93.470s | 1408.928us | 50 | 50 | 100.00 | |
| entropy | 24 | 25 | 96.00 | |||
| alert_handler_entropy | 3543.140s | 323138.501us | 24 | 25 | 96.00 | |
| sig_int_fail | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 101.420s | 2921.259us | 50 | 50 | 100.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 69.220s | 1759.461us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 81.550s | 6679.448us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 92.350s | 1720.726us | 50 | 50 | 100.00 | |
| ping_timeout | 20 | 50 | 40.00 | |||
| alert_handler_ping_timeout | 612.720s | 24874.793us | 20 | 50 | 40.00 | |
| lpg | 91 | 100 | 91.00 | |||
| alert_handler_lpg | 3600.143s | 0.000us | 45 | 50 | 90.00 | |
| alert_handler_lpg_stub_clk | 3600.130s | 0.000us | 46 | 50 | 92.00 | |
| stress_all | 49 | 50 | 98.00 | |||
| alert_handler_stress_all | 4971.190s | 861097.527us | 49 | 50 | 98.00 | |
| alert_handler_entropy_stress_test | 0 | 20 | 0.00 | |||
| alert_handler_entropy_stress | 30.220s | 608.687us | 0 | 20 | 0.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 6.030s | 63.440us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.950s | 18.475us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 27.780s | 360.085us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 27.780s | 360.085us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 8.740s | 126.532us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 12.350s | 130.742us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 60.810s | 1249.235us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 52.370s | 2996.422us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 8.740s | 126.532us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 12.350s | 130.742us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 60.810s | 1249.235us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 52.370s | 2996.422us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 449.110s | 7735.125us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 449.110s | 7735.125us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 449.110s | 7735.125us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 449.110s | 7735.125us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1304.470s | 75714.550us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 35.420s | 3263.419us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 109.560s | 1271.133us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 109.560s | 1271.133us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 449.110s | 7735.125us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 69.220s | 1759.461us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 69.220s | 1759.461us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 69.220s | 1759.461us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 69.220s | 1759.461us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 101.420s | 2921.259us | 50 | 50 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 45 | 50 | 90.00 | |||
| alert_handler_lpg | 3600.143s | 0.000us | 45 | 50 | 90.00 | |
| sec_cm_esc_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 101.420s | 2921.259us | 50 | 50 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 24 | 25 | 96.00 | |||
| alert_handler_entropy | 3543.140s | 323138.501us | 24 | 25 | 96.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 24 | 25 | 96.00 | |||
| alert_handler_entropy | 3543.140s | 323138.501us | 24 | 25 | 96.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 35.420s | 3263.419us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 35.420s | 3263.419us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 35.420s | 3263.419us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 35.420s | 3263.419us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 35.420s | 3263.419us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 35.420s | 3263.419us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 35.420s | 3263.419us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 35.420s | 3263.419us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 35.420s | 3263.419us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 6 | 10 | 60.00 | |||
| alert_handler_stress_all_with_rand_reset | 385.440s | 3603.975us | 6 | 10 | 60.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 26 test runs | |||
| alert_handler_ping_timeout | 34823038757737463449310036000585279668782068040094297495214222215525336570805 | 84 |
UVM_INFO @ 2921280577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 19085170108878449267482707015290590013286044793997756549918895265877785004253 | 99 |
UVM_INFO @ 21616867938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 76427516472416778181673528319614900916830477349917311589509858023796880802882 | 114 |
UVM_INFO @ 5086245509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 97713940627083405526896363293887435508300568827052462648511381328985861936779 | 99 |
UVM_INFO @ 2505330496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 38409673198687739478633788915269564964899799279832633154203850617343979739100 | 87 |
UVM_INFO @ 18233674242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 80653328835166572606574426120002289356687634539133341185394289256991220211307 | 133 |
UVM_INFO @ 17040734162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 114060064753054098554023322530234285659998054312571486082715835845676957712421 | 99 |
UVM_INFO @ 2427026804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 59071501752237860169095439805052056271898391322163788274749365317674148995652 | 84 |
UVM_INFO @ 1049006222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 48131358997920047796421095393835956963049094343514207552369196805075608305421 | 102 |
UVM_INFO @ 13515820355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 68946458025606556340362144189272323934460291244549502353734886228818131834327 | 92 |
UVM_INFO @ 1926266393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 106820602673067403602706505995450101992570815248439030868786672275808327514092 | 84 |
UVM_INFO @ 664821215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 2012114896621016160658246361383219965325217931359336830081721902307874861968 | 87 |
UVM_INFO @ 836144405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 100893224122302997822786404332370432850300870534504363498537514422304602753027 | 87 |
UVM_INFO @ 4343189450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 97121536423591622867771733399743631155023330218354523920693181616529745192230 | 87 |
UVM_INFO @ 6991276813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 43943046552160799844403188115420990328763025321245654267712872491621657646759 | 93 |
UVM_INFO @ 4253853419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 32477511682016670283078616076255332503946332553633178422909615027827297679521 | 99 |
UVM_INFO @ 14912926452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 70150727031204079223877656977779795077369686087929450930203826686443088240619 | 93 |
UVM_INFO @ 4710454858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 96342395846989605425776953575561447882388710462911650211727140806055379402286 | 120 |
UVM_INFO @ 9157089813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 96831407286518971171045395086966237961570320345110548223112096329284133964731 | 93 |
UVM_INFO @ 6181417658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 44087402139866657622766474990015250252574471633794055352932604610150537862634 | 124 |
UVM_INFO @ 127877096368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 58422077139590254398338355413806313644880997313841847532394602208909247044130 | 147 |
UVM_INFO @ 13056160398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 82701314794485644516087604437579850479897060214162018438061963100333390139680 | 87 |
UVM_INFO @ 3016454338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 104333717387649015324163213145969010537986070159596315358663857559511122793323 | 132 |
UVM_INFO @ 17096359499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 82429675760813998966696839893325289714795737417268723144699231833186827218448 | 87 |
UVM_INFO @ 1209796754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 82440128874614815760401941566192445075807369311648349182149204935818630562252 | 112 |
UVM_INFO @ 20411451729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 5038182486754934486600658336117196455554859149860196126312317185546357520115 | 101 |
UVM_INFO @ 30388862219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 20 test runs | |||
| alert_handler_entropy_stress | 85392564290914013382284715449128799429970512684699249554357767873711665990669 | 224 |
UVM_INFO @ 215421852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 102318246525106267963740319127683505870004735459906137422010211526742214735022 | 188 |
UVM_INFO @ 821456974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 36110860110739711850724598507314357350479746233464752239164532519297845090612 | 222 |
UVM_INFO @ 302488854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 15153567253706524089064202543483480985896721859301261865214232386359713824599 | 228 |
UVM_INFO @ 149499521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 22876961321273675806692893683683048649908522389691661446873246405912310218320 | 178 |
UVM_INFO @ 150129491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 39685881294605837942243816587735567188648263894393979952386328939438015109795 | 158 |
UVM_INFO @ 107583201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 65977386773798513106304282587688409352598798425757211429170225229468806573914 | 208 |
UVM_INFO @ 115160588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 1574226430465477746938212160845770049306583486254003456684857643101513391294 | 172 |
UVM_INFO @ 309272143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 94852758429480745287041424658694446338623007437644353956000915632694564566202 | 222 |
UVM_INFO @ 608687147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 96196939683219831162866053237594271766428405760701357748841068598232421720028 | 224 |
UVM_INFO @ 398015960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 36408402238110465240133721110120539196047409286846850499036727685458318849070 | 216 |
UVM_INFO @ 677560642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 45569833685299548049902987154261064729467565768194728812761369930068856517751 | 192 |
UVM_INFO @ 116712116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 62563656116822627618694199185851657174741128430165222543341732371877086376961 | 222 |
UVM_INFO @ 560993152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 88150183392230055673262205587550900257483784276642176949866607730005124573256 | 168 |
UVM_INFO @ 133004017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 78528824951584784179265145524610137658587798912185724869556862752089127606655 | 226 |
UVM_INFO @ 422349743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 13041181830837926559458781244080742076466002538136071518766120994079961303080 | 192 |
UVM_INFO @ 202312513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 88832585901748618716544697041015190698299121494977178226202909353367463504172 | 226 |
UVM_INFO @ 372039650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 22712540460639990418869636507033996818402612673225472469909922681248264571402 | 150 |
UVM_INFO @ 144243107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 2978307570980761878028645478843537089464503628453441159535655169400987705386 | 190 |
UVM_INFO @ 240849580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 55932978157343694243761540563287446487663504358691988128047001518629761767623 | 138 |
UVM_INFO @ 665337000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 7 test runs | |||
| alert_handler_lpg | 115596874818314026293160875853146329369668238876616397196348906465113948928618 | None | ||
| alert_handler_lpg_stub_clk | 9069379447738319709390195345476670970083702904919675237837080166267861512347 | None | ||
| alert_handler_lpg | 95295889430948929298517925965986846584126513790225887941518929651303332284487 | None | ||
| alert_handler_lpg_stub_clk | 34289169759034197074475925063608550502289402957444793857543862933441905103542 | None | ||
| alert_handler_lpg_stub_clk | 4456120922128851618762205141842260957700582336144750356527961159661011005205 | None | ||
| alert_handler_lpg_stub_clk | 61241369070286063383022999072505675498677081227788413814027628030562693825996 | None | ||
| alert_handler_lpg | 61911561937656503050721976897603660783977606155350534274353784634532811024609 | None | ||
| UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 5 test runs | |||
| alert_handler_lpg | 109017838602988049929695469031067440066393121328449428502253456239234251651513 | 80 |
UVM_INFO @ 12035990372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 93359059811317380186299546278830613852357730914922159515386976787719693672422 | 80 |
UVM_INFO @ 439670318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 85072370014146774101413631171100671830669063689966158294346561636378336688077 | 80 |
UVM_INFO @ 934392028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 26431383152688757035137484608660970376065207521356181215330185532052364814105 | 80 |
UVM_INFO @ 517769934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 98441228125043693822520678553732333140645797783187865920416353179651374187254 | 80 |
UVM_INFO @ 541230303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 4 test runs | |||
| alert_handler_stress_all_with_rand_reset | 106484834862553509544511200848815118109876920603319316412712765775525779536871 | 110 |
UVM_INFO @ 3029082416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 37302755370904636690283519388164863975112213053334466082801887187299489196309 | 85 |
UVM_INFO @ 250478406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 49316425045713826926068812826153944909594574271767538739402186449909410560999 | 82 |
UVM_INFO @ 321632989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 32286568437746162598649370883680127520523470387010588129252960581679640397145 | 97 |
UVM_INFO @ 477025083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 1 test run | |||
| alert_handler_entropy | 27892812105901900611060862163038029874523835214240517151324670243205690103802 | 80 |
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.loc_alert_cause_* | 1 test run | |||
| alert_handler_lpg | 55869808689980321184203070494914464501673702041590680519475459395960424632499 | 80 |
UVM_INFO @ 16383885287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_ERROR (cip_base_vseq.sv:858) [alert_handler_sig_int_fail_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) | 1 test run | |||
| alert_handler_stress_all | 84734789650248697565148010182829365278966961785593207777675211554446561174081 | 141 |
UVM_INFO @ 7327721990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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