Simulation Results

Simulation Results: clkmgr

30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
82.74 %

code
79.29 %

assert
93.60 %

func
75.34 %

line
90.93 %

branch
93.43 %

cond
88.22 %

toggle
98.87 %

FSM
25.00 %

Validation stages

V1		65.22%
V2		68.38%
V2S		27.62%
V3		5.00%

15/23 passed

65.22 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	2.470s	96.686us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.590s	48.769us	1	1	100.00
csr_rw				2	5	40.00
	clkmgr_csr_rw	1.220s	14.874us	2	5	40.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	1.950s	41.328us	0	1	0.00
csr_aliasing				1	1	100.00
	clkmgr_csr_aliasing	3.320s	153.420us	1	1	100.00
csr_mem_rw_with_rand_reset				1	5	20.00
	clkmgr_csr_mem_rw_with_rand_reset	1.900s	45.535us	1	5	20.00
regwen_csr_and_corresponding_lockable_csr				3	6	50.00
	clkmgr_csr_rw	1.220s	14.874us	2	5	40.00
	clkmgr_csr_aliasing	3.320s	153.420us	1	1	100.00

80/117 passed

68.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	1.790s	58.240us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	3.620s	161.158us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	1.730s	115.045us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	2.470s	96.686us	10	10	100.00
frequency				0	10	0.00
	clkmgr_frequency	1.490s	33.847us	0	10	0.00
frequency_timeout				0	10	0.00
	clkmgr_frequency_timeout	1.400s	35.058us	0	10	0.00
frequency_overflow				0	10	0.00
	clkmgr_frequency	1.490s	33.847us	0	10	0.00
stress_all				1	10	10.00
	clkmgr_stress_all	8.410s	880.077us	1	10	10.00
alert_test				10	10	100.00
	clkmgr_alert_test	1.980s	62.424us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	10.720s	726.808us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	10.720s	726.808us	25	25	100.00
tl_d_outstanding_access				4	12	33.33
	clkmgr_csr_hw_reset	1.590s	48.769us	1	1	100.00
	clkmgr_csr_rw	1.220s	14.874us	2	5	40.00
	clkmgr_csr_aliasing	3.320s	153.420us	1	1	100.00
	clkmgr_same_csr_outstanding	1.090s	7.259us	0	5	0.00
tl_d_partial_access				4	12	33.33
	clkmgr_csr_hw_reset	1.590s	48.769us	1	1	100.00
	clkmgr_csr_rw	1.220s	14.874us	2	5	40.00
	clkmgr_csr_aliasing	3.320s	153.420us	1	1	100.00
	clkmgr_same_csr_outstanding	1.090s	7.259us	0	5	0.00

V2S

29/105 passed

27.62 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				0	30	0.00
	clkmgr_sec_cm	134.340s	10032.314us	0	5	0.00
	clkmgr_tl_intg_err	3.530s	163.967us	0	25	0.00
shadow_reg_update_error				17	20	85.00
	clkmgr_shadow_reg_errors	2184.400s	200000.000us	17	20	85.00
shadow_reg_read_clear_staged_value				17	20	85.00
	clkmgr_shadow_reg_errors	2184.400s	200000.000us	17	20	85.00
shadow_reg_storage_error				17	20	85.00
	clkmgr_shadow_reg_errors	2184.400s	200000.000us	17	20	85.00
shadowed_reset_glitch				17	20	85.00
	clkmgr_shadow_reg_errors	2184.400s	200000.000us	17	20	85.00
shadow_reg_update_error_with_csr_rw				0	20	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	1.420s	27.852us	0	20	0.00
sec_cm_bus_integrity				0	25	0.00
	clkmgr_tl_intg_err	3.530s	163.967us	0	25	0.00
sec_cm_meas_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency	1.490s	33.847us	0	10	0.00
sec_cm_timeout_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency_timeout	1.400s	35.058us	0	10	0.00
sec_cm_meas_config_shadow				17	20	85.00
	clkmgr_shadow_reg_errors	2184.400s	200000.000us	17	20	85.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	5.680s	322.022us	10	10	100.00
sec_cm_jitter_config_mubi				2	5	40.00
	clkmgr_csr_rw	1.220s	14.874us	2	5	40.00
sec_cm_idle_ctr_redun				0	5	0.00
	clkmgr_sec_cm	134.340s	10032.314us	0	5	0.00
sec_cm_meas_config_regwen				2	5	40.00
	clkmgr_csr_rw	1.220s	14.874us	2	5	40.00
sec_cm_clk_ctrl_config_regwen				2	5	40.00
	clkmgr_csr_rw	1.220s	14.874us	2	5	40.00
prim_count_check				0	5	0.00
	clkmgr_sec_cm	134.340s	10032.314us	0	5	0.00

1/20 passed

5.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
regwen				1	10	10.00
	clkmgr_regwen	1.200s	13.191us	1	10	10.00
stress_all_with_rand_reset				0	10	0.00
	clkmgr_stress_all_with_rand_reset	4.940s	166.563us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:				29 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	63190906062335397166979734208644167869651431434657727644148732048981335893705	75	UVM_INFO @ 12330705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	10391830748174309544345921145307629194255477020005674163052950876734527760319	93	UVM_INFO @ 25131804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	48348822479792602719054438069695929899255104918373624919554908972555844301940	75	UVM_INFO @ 15775831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	74931816229969840399213771912244202862483888394357602602490169441743707289332	76	UVM_INFO @ 5899724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	88884052743384415236989474361193887073692149059178164086623253824464327971788	75	UVM_INFO @ 5169277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	32284502078929212071266656899073274462036570369364736539365101225986518177074	76	UVM_INFO @ 11348357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	49666898471911295655426495955910037903003781285468821256181625323405212337072	75	UVM_INFO @ 19778573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	41454742055288098677782558050292698324556789686610275005327408495657829809573	76	UVM_INFO @ 22837307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	72242689320005789538422051363597622471970573846320541402354789279919243194503	109	UVM_INFO @ 93757109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	52184129750382240339935147736261282001734243843470576988141068334664866933428	75	UVM_INFO @ 3658488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	20634035282387151043979866274762814977754219898698839260553941637767760118855	78	UVM_INFO @ 17125073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	59530810101775431821643516876862908589745891118939508883590927877463259946093	86	UVM_INFO @ 12072282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	6870939650570809010274677564736473847899780057832829021284754820037206686391	75	UVM_INFO @ 3462019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	25501227332831043402934906878621446721629856411797191974942891296002097297318	78	UVM_INFO @ 2556013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	71399822813546713813835561694742844445587193499255299477340858554321068030029	75	UVM_INFO @ 27852217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	50369611271004399260116678108681493494357583921358796538185973884720631398537	78	UVM_INFO @ 13335297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	47222614465268485761728705554056402351628351475478119646585122638545092071120	75	UVM_INFO @ 4927373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	7841792180418463275246535108738374636613499716288505368274511965347523930439	75	UVM_INFO @ 9784935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	70378020313771722556585394906541987951265693216408132479963595393215195355409	75	UVM_INFO @ 2691499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	55700344934176664169657692945892477233068390419111199415519229483035538193001	75	UVM_INFO @ 3700856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	85792422301087923313313698717614497041057003965538911249654855246400068940334	119	UVM_INFO @ 163967078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	99217160016593955209236641048331889460226852468991369381186645934861157907679	89	UVM_INFO @ 10322294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	107556255910323157500766753161811366715734865861994988938368690506779071257531	75	UVM_INFO @ 8295753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	52777306918942383891321901978618920236418771931008105313674244966061499647993	85	UVM_INFO @ 6909585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	63743922714707979895448729009508837597608275043469753645569460968040865441113	75	UVM_INFO @ 4267024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	35331112629626990826566807290215070254606382292937130983361224409574484882493	85	UVM_INFO @ 3675931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	46332692787455868208728607642967420248506391877070516804612492617702018463899	112	UVM_INFO @ 34991965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	13282848649873322672039756400675402461198469100250713430518113972977826155536	89	UVM_INFO @ 26914136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	51018369769565326937847493450813674655148001049515128076835619556906512266702	86	UVM_INFO @ 8896310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:				23 test runs
	clkmgr_csr_mem_rw_with_rand_reset	18017944993689079131185687549830152213629657259195115249995056439712960761271	82	UVM_INFO @ 45535130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	102294210396739466600422951955922134043952518137947097599207214370605709839049	131	UVM_INFO @ 205515329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	96369647106605318262329674292892295417458764054686292555278114160566690465396	75	UVM_INFO @ 4008769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	115665061753999637788131971104457598679963569282747213267788891805832112700080	75	UVM_INFO @ 2851275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	16878008654625085248322332479056545541945122721887907440705290537016886749866	97	UVM_INFO @ 27608916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	78968375856728421852321883406067788976939798151137954970091514794096647759683	76	UVM_INFO @ 8792080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	7686994729188099010829334559775756327653979253232380577636544491187376638893	93	UVM_INFO @ 25750594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	44013041263469136231387185900839888321420745232604803955637587528411045212059	82	UVM_INFO @ 28352363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	65184032242296913553921714579016349861279606887160799934490682837316241770125	93	UVM_INFO @ 16373691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	115076822945712577282742470226241551107829700850310687109594167384551164422987	75	UVM_INFO @ 5025577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	75645200187358122555650454251926749915293193840946248104094611570511459639882	93	UVM_INFO @ 49073800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	28085700600477210319181366073500923215469094302759986314503146012451257619733	75	UVM_INFO @ 8036804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	91524182693088539576896043046410480761783642994013835377025046092562386412118	75	UVM_INFO @ 11810073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	103508044878548933286128791785521636088497257154045088072610781468097030022327	78	UVM_INFO @ 2781567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	86690142021846297801167242431689051519310849095284171439749981910705348858172	75	UVM_INFO @ 7274204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	75872238785788157827575496523861874636515684192084610745303244232086206195564	82	UVM_INFO @ 9415258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	81921470518235750952286828807527186361385159763910504430167945754491475109318	75	UVM_INFO @ 3736083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	48608500833714057242098559659322628290579708364832627586758565014610947200834	75	UVM_INFO @ 5768908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	85852811458199199081544269523830926870675474312692967757319018831671013683337	75	UVM_INFO @ 3331792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	85411408369485929680493374302659322968727935659685835058387018536457370926982	93	UVM_INFO @ 35770793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	65211821176468571172134934916367506699454443946228922265246226268299232320692	94	UVM_INFO @ 12203413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	83598621394603041167008628756238080418789856658190207443840296685424392860768	78	UVM_INFO @ 6069670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	27824293740898296596211913246799938504135748118966932876460018811699883884403	75	UVM_INFO @ 3120129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b				21 test runs
	clkmgr_frequency_timeout	6061716844218234848901573852788081110856744106206887831645493383735333896968	78	UVM_INFO @ 3618790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	12405350914391775327110118949564327638615648367599964389090787636444564776287	105	UVM_INFO @ 21784995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	88010971406663145542335292048857322826201843777070579128358447910262212616927	78	UVM_INFO @ 4435682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	114256546932343824623669589210235396083491880514086178442282384957405922725366	143	UVM_INFO @ 144037437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	64335469861496515457464116259654367684060549058042476981274624433244280102316	78	UVM_INFO @ 4586399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	2937482067885820683514105243642748877765922865988289895724530513257081539256	78	UVM_INFO @ 3267192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	47073169136621953550353466214570613217766633712920123472055829826882934598195	217	UVM_INFO @ 128307154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	87454261937359269355363532718666427734984247700536249081551927137291871853161	78	UVM_INFO @ 3995919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	74732154940273595704570135087095938199834094936915916898287610180477264371571	79	UVM_INFO @ 98485284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	17168210635036497645003798099333270893673778108245049613728576923905190162235	110	UVM_INFO @ 880076667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	38840293234219365588663438816745757557846910886336705471172010167033800513329	77	UVM_INFO @ 2236716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	41372535168646443429160535288955968323186242225823602005125916725193017386873	79	UVM_INFO @ 5050979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	65420168356390471320662809828062098073946009440744360508120156289293323407861	78	UVM_INFO @ 211337453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	7086328574469492405472689126001801046540530141604275553712900436541032359649	77	UVM_INFO @ 4908427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	102962237813275309884535432377182301951579613891230358452181112441436852116457	77	UVM_INFO @ 12500649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	67687558996121157656541417792696011367225831868100331994683466172258919050428	77	UVM_INFO @ 35058217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	11452594002994925795124884203990117597125802685225619709882634281101651629694	78	UVM_INFO @ 7143630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	87592155186080427551055483709523990242936702425244053427975780552605632053237	78	UVM_INFO @ 3687572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	13339834844185415692272283218349420712769395951181699039390759562741004564988	77	UVM_INFO @ 15141342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	24868291441300801670567325847820514413362357055892763782491664933470967704166	78	UVM_INFO @ 3350188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	13961956191769355158827742805075474043958347985668433008976091890443786684606	124	UVM_INFO @ 166563229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b				18 test runs
	clkmgr_frequency	76543155371554096473078165788984213004191292039403793165206126873526163831518	75	UVM_INFO @ 4698691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	16339852461368959759730348115976772142274890919785213353598279155835539679014	78	UVM_INFO @ 14704311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	24692411034692048613985769108324730656074352104251919187452154234223609178925	76	UVM_INFO @ 10593192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	105575970299900190135529558538664276965935583417282668840531079973003522300947	76	UVM_INFO @ 6844383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	29688134258731101169244711538256946431414688393939543483273815047099029937855	78	UVM_INFO @ 25464453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	19647597508028059228655682859946988294210687702457130104437099748695859267707	75	UVM_INFO @ 8406247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	89718674587025937059756734180564675335255576949323021527337967530797239537695	78	UVM_INFO @ 8686166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	1177196884098474048786875665433190485663120093922396586000054878688579248137	100	UVM_INFO @ 67440113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	6325346102345147674379657329341246471801534670954447746295334085457555172674	75	UVM_INFO @ 33846587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	23818612552732648902772758219277055492600944719886940223787394380956243736135	75	UVM_INFO @ 12470198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	69555248779856759785248433234402967228088417145433516374150642692668715397791	76	UVM_INFO @ 6537150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	14469186565427880720847670368360626630371670594803448292986276934837647456500	99	UVM_INFO @ 55319803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	34889781974171576016319229817461459937952582516808629929850521965506230759749	75	UVM_INFO @ 11098307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	98030855023032109098044908176551601559755603160552080048883439142765099853759	78	UVM_INFO @ 9537822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	49650688932804267188924028614885212866781962097864110080942585482647309726805	75	UVM_INFO @ 6411777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	21925454228998963049730183662687692703597036205127102046248226873067646188168	77	UVM_INFO @ 60611175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	93564708988998325461785987741131256777283015267795177032574927803819772017507	76	UVM_INFO @ 6759673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	107030408844962217839520969760423167358178596227877215995692212835750790886115	76	UVM_INFO @ 39589743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				5 test runs
	clkmgr_same_csr_outstanding	85547570556609203993188008663163295218773408559568087985958357813363900317397	75	UVM_INFO @ 11770392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	4335966047161439122694580453653487755688736789633085958651910013283015206472	75	UVM_INFO @ 7258923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	69232396966612777505994967990586786114521529902154894965016127214700323750886	75	UVM_INFO @ 4763902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	51435952157588094743960560882551427968630886504496358977145643643244918792510	75	UVM_INFO @ 5279329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	95501188011562902949538459574687769761577604017216214739282952150276116775713	75	UVM_INFO @ 5295919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en				4 test runs
	clkmgr_regwen	89692273212088766439028199247945135321848429960282783066114781507465312180368	74	UVM_INFO @ 3323702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	3835473245047315575510863028185644492388243411695674878112052424638579519727	74	UVM_INFO @ 4519119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	16934756162810104852864877494951105552757624890481557794288614457274334673932	74	UVM_INFO @ 3160074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	98083942184276805353895077031770968376723058028288879171653548448832707135566	74	UVM_INFO @ 9028126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault				4 test runs
	clkmgr_sec_cm	65067598516305400772661156208236325054323410485316975993254922042864403187777	85	UVM_INFO @ 10032314131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	67503528848422199513505084048908785107294540363723146536424093914137548882428	83	UVM_INFO @ 10009212880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	19826554962600735600023816155203397415818365706028813138594145233874144431134	93	UVM_INFO @ 10021765711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	86125539096898303161942638963380020437841781649325097975932352605582103471113	90	UVM_INFO @ 10078621987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed				4 test runs
	clkmgr_regwen	22853003232144667799759695536611978799962971890514337801075015041094089888000	74	UVM_INFO @ 13190508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	55946528341505796209074369750488161173266283174508313365174499196641753620132	74	UVM_INFO @ 5385028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	50490748729989045788517456446895930063829409576392605180057757080571102471849	74	UVM_INFO @ 3053874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	3338934445209988273123550841890563859065136753654925308567080004548765007590	74	UVM_INFO @ 6728399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				3 test runs
	clkmgr_shadow_reg_errors	91497681159962886321975809217232362422236717861277666349254818751994731310984	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	111067352422244741495615562603438681092394230532618013001620099568394564432510	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	27207864146301781516002048990996891599359235193381330065682062744969799260541	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:				1 test run
	clkmgr_csr_bit_bash	108519099417419976058623495562035091373225111008168730516230509915026344901071	75	UVM_INFO @ 41328468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				1 test run
	clkmgr_sec_cm	90201890390653041319392469270924764741548398357636676299392310655961860470879	127	UVM_INFO @ 53953834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en				1 test run
	clkmgr_regwen	62016159522258479602707153441992172056916074682064515426649988113597523353030	74	UVM_INFO @ 10305336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---