Simulation Results: csrng

 
30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.33 %
  • code
  • 96.20 %
  • assert
  • 96.51 %
  • func
  • 90.27 %
  • block
  • 98.53 %
  • line
  • 99.54 %
  • branch
  • 96.38 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.09%
V2S
99.14%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 5.000s 199.576us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 32.000s 29.867us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 33.000s 60.224us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 68.000s 1394.934us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 39.000s 297.758us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 32.000s 22.816us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 33.000s 60.224us 5 5 100.00
csrng_csr_aliasing 39.000s 297.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 40.000s 427.893us 200 200 100.00
alerts 500 500 100.00
csrng_alert 61.000s 4569.613us 500 500 100.00
err 500 500 100.00
csrng_err 32.000s 25.185us 500 500 100.00
cmds 1 25 4.00
csrng_cmds 83.000s 4044.211us 1 25 4.00
life cycle 1 25 4.00
csrng_cmds 83.000s 4044.211us 1 25 4.00
stress_all 24 25 96.00
csrng_stress_all 613.000s 27099.209us 24 25 96.00
intr_test 10 10 100.00
csrng_intr_test 32.000s 37.350us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 33.000s 133.838us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 22.000s 1768.255us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 22.000s 1768.255us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 32.000s 29.867us 1 1 100.00
csrng_csr_rw 33.000s 60.224us 5 5 100.00
csrng_csr_aliasing 39.000s 297.758us 1 1 100.00
csrng_same_csr_outstanding 32.000s 108.454us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 32.000s 29.867us 1 1 100.00
csrng_csr_rw 33.000s 60.224us 5 5 100.00
csrng_csr_aliasing 39.000s 297.758us 1 1 100.00
csrng_same_csr_outstanding 32.000s 108.454us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
csrng_sec_cm 13.000s 50.268us 5 5 100.00
csrng_tl_intg_err 20.000s 1204.994us 25 25 100.00
sec_cm_config_regwen 20 30 66.67
csrng_regwen 32.000s 80.712us 15 25 60.00
csrng_csr_rw 33.000s 60.224us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 61.000s 4569.613us 500 500 100.00
sec_cm_intersig_mubi 24 25 96.00
csrng_stress_all 613.000s 27099.209us 24 25 96.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 40.000s 427.893us 200 200 100.00
csrng_err 32.000s 25.185us 500 500 100.00
csrng_sec_cm 13.000s 50.268us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 40.000s 427.893us 200 200 100.00
csrng_err 32.000s 25.185us 500 500 100.00
csrng_sec_cm 13.000s 50.268us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 40.000s 427.893us 200 200 100.00
csrng_err 32.000s 25.185us 500 500 100.00
csrng_sec_cm 13.000s 50.268us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 40.000s 427.893us 200 200 100.00
csrng_err 32.000s 25.185us 500 500 100.00
csrng_sec_cm 13.000s 50.268us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 40.000s 427.893us 200 200 100.00
csrng_err 32.000s 25.185us 500 500 100.00
csrng_sec_cm 13.000s 50.268us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 61.000s 4569.613us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 40.000s 427.893us 200 200 100.00
csrng_err 32.000s 25.185us 500 500 100.00
sec_cm_constants_lc_gated 24 25 96.00
csrng_stress_all 613.000s 27099.209us 24 25 96.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 61.000s 4569.613us 500 500 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
csrng_tl_intg_err 20.000s 1204.994us 25 25 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 40.000s 427.893us 200 200 100.00
csrng_err 32.000s 25.185us 500 500 100.00
csrng_sec_cm 13.000s 50.268us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 40.000s 427.893us 200 200 100.00
csrng_err 32.000s 25.185us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 40.000s 427.893us 200 200 100.00
csrng_err 32.000s 25.185us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 40.000s 427.893us 200 200 100.00
csrng_err 32.000s 25.185us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 40.000s 427.893us 200 200 100.00
csrng_err 32.000s 25.185us 500 500 100.00
csrng_sec_cm 13.000s 50.268us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 40.000s 427.893us 200 200 100.00
csrng_err 32.000s 25.185us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
csrng_stress_all_with_rand_reset 3601.000s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 21 test runs
csrng_cmds 61019712249549347168554699076515528356826677667772562331762524819568633281217 100
UVM_INFO @ 63927118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 111453853706526631380539160024098275358847660204606705609037806393654440508981 100
UVM_INFO @ 362918815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 54010048366465727985048947088771155053361164585497115326443353473404145289734 100
UVM_INFO @ 185349192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 24185278057627134063670966638423423611866298679747637335825045344753296171837 100
UVM_INFO @ 81013973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 93508432539098125890910905523894020608590157595356981616700164319922419251441 100
UVM_INFO @ 223971092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 31392602157330759855048082151567757116095882839560348480960731626097882556651 100
UVM_INFO @ 397596616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 115083641347893748010157258160259042341906478427452508911592030945023770921173 100
UVM_INFO @ 122413952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 60616050100208972461870892423314967063077628729457450191743308209259875639202 100
UVM_INFO @ 166262020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 21046553082222322051883968772263603662866006873533692815788666743305181143308 100
UVM_INFO @ 111443603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 94023027426981785192570871947551488799875341166314471217105935328938365768521 110
UVM_INFO @ 407439502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 36776263845734674591864626556359118020747183224032361990012899309350614273852 100
UVM_INFO @ 75328660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 10691587058176502725103342894360717660862071154297143269321878336298419446988 100
UVM_INFO @ 111370325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 105837495597820174259810051282509306837511450882673726326149871801597389060928 100
UVM_INFO @ 66995094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 45161061915506257353560372270106941148062927223690525447821665971772194219729 100
UVM_INFO @ 186861488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 59917215679721169956017049275693742320278390892666633621827928592610761542172 100
UVM_INFO @ 697677334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 89957451753925600577630686722448626455583406138939342750659962200240601688543 100
UVM_INFO @ 98881388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 67128549020013162761352891704000439483660424945823628572779335524282305518294 100
UVM_INFO @ 90662490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 103654372577311661531576428929353839281410755544750219742787640030958617273869 100
UVM_INFO @ 15486153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 101543594549424453865388158160035232007959437255691252072062547029266400854907 110
UVM_INFO @ 717278653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 29877419116158582063133348032154421318452455537556959187463100894726156277275 100
UVM_INFO @ 80605989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 47940330899219028299798864710381938917860887862934519945968604009409553809902 100
UVM_INFO @ 42635387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 9 test runs
csrng_stress_all_with_rand_reset 51936240051170154180311437166165177231456994532023317317754869356493158224420 None
csrng_stress_all_with_rand_reset 105274296623807237019681972859601381605894998624433815478745039082595097092373 None
csrng_stress_all_with_rand_reset 112774638870274869467983783523122604907950647107801024066018559297272481934689 None
csrng_stress_all_with_rand_reset 88397676658930036964686773794897792928093505722466125519531288767721520015056 None
csrng_stress_all_with_rand_reset 23107772602307532172729040155406871065385000996502709415958995141843980074172 None
csrng_stress_all_with_rand_reset 53889797260526735042212130611402744838660478066253852341337408509414343592885 None
csrng_stress_all_with_rand_reset 5937377514466986374937297713642118718161624541108989188690041229344295261287 None
csrng_stress_all_with_rand_reset 68141961582551673869029423925117368991712677706327311652388710903210599772327 None
csrng_stress_all_with_rand_reset 14379458102663196460275928199624666894603701198075685372289645465953384670737 None
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 8 test runs
csrng_regwen 105286937345142606820445095300011161091306030077380646491962430483096858584515 99
UVM_INFO @ 27965071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 58997639456535458171294889978383405869050251221008356284974134022556279831652 99
UVM_INFO @ 12961206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 64575525349587350226158388810772722291081543879300832412145424200209487882298 99
UVM_INFO @ 8058550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 9486857971882841447519137852643816573390982501761645226196699088311259354597 99
UVM_INFO @ 1999935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 98598089767192593132863926934390203123049038269518353489316630649912440272658 99
UVM_INFO @ 2524834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 30104485446590824182769781659658617227663768897063604663024196902118466855040 99
UVM_INFO @ 2883342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 88265189827092967572202636200262673475339036298503172639486964603468133891659 99
UVM_INFO @ 12668111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 80412035840424943447070882958370332418830960260808521621689304316300715248060 99
UVM_INFO @ 11178751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: csrng_reg_block.genbits 2 test runs
csrng_cmds 65545742336305364767591104412461857465309470688384814152698735456335454787355 103
UVM_INFO @ 48226712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 111304870323381728505350337975954806618200498438984179822953391352898439810852 103
UVM_INFO @ 270921955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 2 test runs
csrng_regwen 39621500322621421764118626489498387980488171210233884009557444897364688931741 99
UVM_INFO @ 15936625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 77141049744606243365434166277271169605008493111063233715028569045048032129383 99
UVM_INFO @ 12752954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 1 test run
csrng_stress_all_with_rand_reset 22793945694358609730985243223848544800952378822574163420327471437932642341265 104
UVM_INFO @ 25043990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all 102000571581297108795535531849886482817144642225585589009018867273005086390695 106
UVM_INFO @ 315138472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:640) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*]) 1 test run
csrng_cmds 4937603281653834674737679515532446583942043744872343500354088457737643738041 109
UVM_INFO @ 33296079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---