Simulation Results: edn/edn0

 
30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.04 %
  • code
  • 95.28 %
  • assert
  • 98.23 %
  • func
  • 58.60 %
  • block
  • 96.95 %
  • line
  • 98.68 %
  • branch
  • 93.23 %
  • toggle
  • 89.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.52%
V2S
100.00%
V3
73.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 2.000s 19.852us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 17.490us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 2.000s 57.670us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.000s 508.521us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 4.000s 242.072us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 56.154us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 2.000s 57.670us 5 5 100.00
edn_csr_aliasing 4.000s 242.072us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 76.000s 6307.595us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 76.000s 6307.595us 100 100 100.00
genbits 100 100 100.00
edn_genbits 76.000s 6307.595us 100 100 100.00
interrupts 20 20 100.00
edn_intr 2.000s 30.378us 20 20 100.00
alerts 200 200 100.00
edn_alert 3.000s 48.496us 200 200 100.00
errs 100 100 100.00
edn_err 3.000s 129.185us 100 100 100.00
disable 91 100 91.00
edn_disable 6.000s 500.000us 49 50 98.00
edn_disable_auto_req_mode 6.000s 500.000us 42 50 84.00
stress_all 30 30 100.00
edn_stress_all 9.000s 544.090us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 2.000s 22.000us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 2.000s 15.987us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 6.000s 159.688us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 6.000s 159.688us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.000s 17.490us 1 1 100.00
edn_csr_rw 2.000s 57.670us 5 5 100.00
edn_csr_aliasing 4.000s 242.072us 1 1 100.00
edn_same_csr_outstanding 3.000s 41.957us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.000s 17.490us 1 1 100.00
edn_csr_rw 2.000s 57.670us 5 5 100.00
edn_csr_aliasing 4.000s 242.072us 1 1 100.00
edn_same_csr_outstanding 3.000s 41.957us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 11.000s 706.732us 5 5 100.00
edn_tl_intg_err 11.000s 526.244us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 2.000s 80.714us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 3.000s 48.496us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 11.000s 706.732us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 11.000s 706.732us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 11.000s 706.732us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 11.000s 706.732us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 3.000s 48.496us 200 200 100.00
edn_sec_cm 11.000s 706.732us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 3.000s 48.496us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 11.000s 526.244us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 22 30 73.33
edn_stress_all_with_rand_reset 110.000s 9118.903us 22 30 73.33

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 7 test runs
edn_stress_all_with_rand_reset 114085056779420334945128644597395690449665605195902527112434874428183272359110 175
UVM_INFO @ 246793355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 87987145314471008718025412667266798461478008641012769662870724148998702457520 247
UVM_INFO @ 2205141133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 20285837932796182839541595789188907548500254370033372776001373170482608854331 231
UVM_INFO @ 2029279907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 46790490914484869185268976136132505911688532157075517960854571853709026713145 172
UVM_INFO @ 317865736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 45137689394801872507073336725206356108651588825465174630044722809560740152631 141
UVM_INFO @ 115775008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 65437465867162247719067678332909055193034192898484906262691926578710387686756 148
UVM_INFO @ 1145302730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 66554966534921520957442332115318279864367349523246169114131889620080442747019 232
UVM_INFO @ 2224392899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:431) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 5 test runs
edn_disable_auto_req_mode 112794542541265952275077524797489094061274309078598325743282216000062066812166 103
UVM_INFO @ 58235850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 47112849238028488937547473753080904228253663468077225816846482584961356327057 103
UVM_INFO @ 31990051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 61591561187905396563121446857116470211972014284451822500650370085867490378918 103
UVM_INFO @ 25009994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 106686492107077693400014164039222103816282788966877614627169202554079586780363 103
UVM_INFO @ 51821939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 85570218741114248906513619860824885106592338137922034487472530548963244432779 103
UVM_INFO @ 41249359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
edn_disable_auto_req_mode 11981472790785451971562187671048079569515005321456957122217876681975290910360 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable 85104799804895000785761990969545393272986496827548562322697512578640573485772 98
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 45650984828597889308684924641696386721864025894423736307307937700122787135495 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 44836311766204409368356037574623493239111921036063201672254644241391648668761 105
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_csrng_agent_*/csrng_agent_cov.sv, Line: *):(Time: * PS + *) Sampled value (INV) for coverpoint (worklib.csrng_agent_pkg::csrng_agent_cov::m_device_cmd_cg@*_*.csrng_cmd_cp) is an illegal value. 1 test run
edn_stress_all_with_rand_reset 32649848074580301984417227939300082878570181697122147201576399145683900265957 159
UVM_INFO @ 130835734 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Running run_tl_errors_vseq 2/138
UVM_INFO @ 152304950 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Running run_tl_errors_vseq 3/138
UVM_INFO @ 258508182 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Running run_tl_errors_vseq 4/138
UVM_INFO @ 296824202 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Running run_tl_errors_vseq 5/138