Simulation Results: edn/edn1

 
30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.68 %
  • code
  • 95.91 %
  • assert
  • 98.70 %
  • func
  • 92.44 %
  • line
  • 98.41 %
  • branch
  • 94.16 %
  • cond
  • 94.23 %
  • toggle
  • 96.15 %
  • FSM
  • 96.59 %
Validation stages
V1
100.00%
V2
98.68%
V2S
100.00%
V3
86.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.360s 18.165us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.040s 24.934us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.130s 50.960us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.370s 635.607us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.630s 21.966us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.900s 22.677us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.130s 50.960us 5 5 100.00
edn_csr_aliasing 1.630s 21.966us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 4.110s 157.403us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 4.110s 157.403us 100 100 100.00
genbits 100 100 100.00
edn_genbits 4.110s 157.403us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.440s 20.689us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.870s 112.724us 200 200 100.00
errs 100 100 100.00
edn_err 1.550s 21.839us 100 100 100.00
disable 92 100 92.00
edn_disable 1.260s 12.969us 50 50 100.00
edn_disable_auto_req_mode 7.340s 500.000us 42 50 84.00
stress_all 30 30 100.00
edn_stress_all 5.610s 287.077us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.220s 20.015us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.160s 30.243us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 5.000s 1702.095us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 5.000s 1702.095us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.040s 24.934us 1 1 100.00
edn_csr_rw 1.130s 50.960us 5 5 100.00
edn_csr_aliasing 1.630s 21.966us 1 1 100.00
edn_same_csr_outstanding 1.590s 33.795us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.040s 24.934us 1 1 100.00
edn_csr_rw 1.130s 50.960us 5 5 100.00
edn_csr_aliasing 1.630s 21.966us 1 1 100.00
edn_same_csr_outstanding 1.590s 33.795us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 7.030s 489.678us 5 5 100.00
edn_tl_intg_err 2.530s 273.675us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.320s 21.475us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.870s 112.724us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.030s 489.678us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.030s 489.678us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.030s 489.678us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.030s 489.678us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.870s 112.724us 200 200 100.00
edn_sec_cm 7.030s 489.678us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.870s 112.724us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 2.530s 273.675us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 26 30 86.67
edn_stress_all_with_rand_reset 111.440s 10754.511us 26 30 86.67

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 41497115580385717016698010497285857990686469807126070636371369252654740352511 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 33008883734989362560622076711738826787843383653584956936795562999256900631943 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 86471390978854128056986148738186838587118876388976976384058714558033100966307 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 66380743060439175079320725495794654673511958886006419580827530088986681053468 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 4673449049190751943419330890891060044404183504443893804529936426880848521215 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
edn_stress_all_with_rand_reset 10943122361378152422097520634048798905814727525714323875219157109437350001391 155
UVM_INFO @ 494445834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 107949430201510674594143917399861097871366799051908083061408300753301935326651 211
UVM_INFO @ 2588281539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 83699094407068692590659357901075954063742501754845013682520107387494592503850 137
UVM_INFO @ 118905333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 3 test runs
edn_disable_auto_req_mode 79385049506387744885665993921934320846037258973376290076350272692768120745634 88
UVM_INFO @ 24433911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 2792240696065822680970037596831677109388223130428920602094116315214970121686 88
UVM_INFO @ 62188703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 92914296768579015331230380818319645536577808560294894318392763766512973608757 88
UVM_INFO @ 22888287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 27187158897375392502311333698555051206063951861325706982954630476792160124138 169
UVM_INFO @ 10754511414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---