Simulation Results: hmac

 
30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 98.12 %
  • code
  • 96.11 %
  • assert
  • 98.26 %
  • func
  • 100.00 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 21.000s 5274.335us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 31.272us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 2.000s 28.033us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 18.000s 6693.285us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 8.000s 2861.037us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 20.000s 5971.039us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 2.000s 28.033us 5 5 100.00
hmac_csr_aliasing 8.000s 2861.037us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 111.000s 9656.621us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 124.000s 14281.167us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 308.000s 8163.886us 30 30 100.00
hmac_test_sha384_vectors 658.000s 16190.160us 75 75 100.00
hmac_test_sha512_vectors 664.000s 17141.951us 75 75 100.00
hmac_test_hmac256_vectors 22.000s 828.867us 50 50 100.00
hmac_test_hmac384_vectors 24.000s 438.160us 60 60 100.00
hmac_test_hmac512_vectors 28.000s 928.670us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 56.000s 942.750us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 374.000s 26373.347us 10 10 100.00
error 10 10 100.00
hmac_error 122.000s 30169.161us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 146.000s 69318.974us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 21.000s 5274.335us 10 10 100.00
hmac_long_msg 111.000s 9656.621us 10 10 100.00
hmac_back_pressure 124.000s 14281.167us 25 25 100.00
hmac_datapath_stress 374.000s 26373.347us 10 10 100.00
hmac_burst_wr 56.000s 942.750us 50 50 100.00
hmac_stress_all 1231.000s 19784.735us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 21.000s 5274.335us 10 10 100.00
hmac_long_msg 111.000s 9656.621us 10 10 100.00
hmac_back_pressure 124.000s 14281.167us 25 25 100.00
hmac_datapath_stress 374.000s 26373.347us 10 10 100.00
hmac_wipe_secret 146.000s 69318.974us 10 10 100.00
hmac_test_sha256_vectors 308.000s 8163.886us 30 30 100.00
hmac_test_sha384_vectors 658.000s 16190.160us 75 75 100.00
hmac_test_sha512_vectors 664.000s 17141.951us 75 75 100.00
hmac_test_hmac256_vectors 22.000s 828.867us 50 50 100.00
hmac_test_hmac384_vectors 24.000s 438.160us 60 60 100.00
hmac_test_hmac512_vectors 28.000s 928.670us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 21.000s 5274.335us 10 10 100.00
hmac_long_msg 111.000s 9656.621us 10 10 100.00
hmac_back_pressure 124.000s 14281.167us 25 25 100.00
hmac_datapath_stress 374.000s 26373.347us 10 10 100.00
hmac_burst_wr 56.000s 942.750us 50 50 100.00
hmac_error 122.000s 30169.161us 10 10 100.00
hmac_wipe_secret 146.000s 69318.974us 10 10 100.00
hmac_test_sha256_vectors 308.000s 8163.886us 30 30 100.00
hmac_test_sha384_vectors 658.000s 16190.160us 75 75 100.00
hmac_test_sha512_vectors 664.000s 17141.951us 75 75 100.00
hmac_test_hmac256_vectors 22.000s 828.867us 50 50 100.00
hmac_test_hmac384_vectors 24.000s 438.160us 60 60 100.00
hmac_test_hmac512_vectors 28.000s 928.670us 75 75 100.00
hmac_stress_all 1231.000s 19784.735us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1231.000s 19784.735us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 2.000s 12.122us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 2.000s 14.198us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 10.000s 70.519us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 10.000s 70.519us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 2.000s 31.272us 1 1 100.00
hmac_csr_rw 2.000s 28.033us 5 5 100.00
hmac_csr_aliasing 8.000s 2861.037us 1 1 100.00
hmac_same_csr_outstanding 3.000s 204.091us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 2.000s 31.272us 1 1 100.00
hmac_csr_rw 2.000s 28.033us 5 5 100.00
hmac_csr_aliasing 8.000s 2861.037us 1 1 100.00
hmac_same_csr_outstanding 3.000s 204.091us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 2.000s 498.372us 5 5 100.00
hmac_tl_intg_err 8.000s 147.041us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 8.000s 147.041us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 21.000s 5274.335us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.000s 976.720us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 839.000s 195174.566us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.000s 41.045us 1 1 100.00