Simulation Results: keymgr_dpe

 
30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 66.44 %
  • code
  • 84.13 %
  • assert
  • 97.14 %
  • func
  • 18.04 %
  • block
  • 98.11 %
  • line
  • 98.79 %
  • branch
  • 93.68 %
  • toggle
  • 62.50 %
  • FSM
  • 81.54 %
Validation stages
V1
91.30%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 10 80.00
keymgr_dpe_smoke 324.000s 38422.573us 8 10 80.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 1.000s 21.516us 1 1 100.00
csr_rw 5 5 100.00
keymgr_dpe_csr_rw 2.000s 286.981us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 7.000s 497.429us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 4.000s 137.394us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 2.000s 46.811us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_dpe_csr_rw 2.000s 286.981us 5 5 100.00
keymgr_dpe_csr_aliasing 4.000s 137.394us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 10 10 100.00
keymgr_dpe_intr_test 2.000s 9.653us 10 10 100.00
alert_test 10 10 100.00
keymgr_dpe_alert_test 2.000s 34.921us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_dpe_tl_errors 6.000s 3040.616us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_dpe_tl_errors 6.000s 3040.616us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_dpe_csr_hw_reset 1.000s 21.516us 1 1 100.00
keymgr_dpe_csr_rw 2.000s 286.981us 5 5 100.00
keymgr_dpe_csr_aliasing 4.000s 137.394us 1 1 100.00
keymgr_dpe_same_csr_outstanding 3.000s 56.515us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_dpe_csr_hw_reset 1.000s 21.516us 1 1 100.00
keymgr_dpe_csr_rw 2.000s 286.981us 5 5 100.00
keymgr_dpe_csr_aliasing 4.000s 137.394us 1 1 100.00
keymgr_dpe_same_csr_outstanding 3.000s 56.515us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
keymgr_dpe_sec_cm 18.000s 1251.156us 5 5 100.00
keymgr_dpe_tl_intg_err 8.000s 2124.414us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 5.000s 145.800us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_dpe_shadow_reg_errors 5.000s 145.800us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 5.000s 145.800us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_dpe_shadow_reg_errors 5.000s 145.800us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 8.000s 285.561us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_dpe_sec_cm 18.000s 1251.156us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_dpe_sec_cm 18.000s 1251.156us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert recov_operation_err has unexpected timeout error 2 test runs
keymgr_dpe_smoke 66633447370382864202610509508820815262738320216289240697969928809445902125046 775
UVM_INFO @ 181992938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_dpe_smoke 46828075609031882150000801676565734925091900396287234476625056322200636046094 4136
UVM_INFO @ 3293350350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---