Simulation Results: kmac/masked

 
30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.70 %
  • code
  • 94.12 %
  • assert
  • 97.98 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.10 %
  • cond
  • 94.78 %
  • toggle
  • 99.89 %
  • FSM
  • 79.58 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
kmac_smoke 72.860s 22118.912us 20 20 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.020s 14.806us 1 1 100.00
csr_rw 5 5 100.00
kmac_csr_rw 1.480s 95.086us 5 5 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 12.100s 568.897us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.340s 289.314us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
kmac_csr_mem_rw_with_rand_reset 2.440s 330.416us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
kmac_csr_rw 1.480s 95.086us 5 5 100.00
kmac_csr_aliasing 3.340s 289.314us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.860s 20.443us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.910s 73.538us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 20 20 100.00
kmac_long_msg_and_output 5447.320s 135470.269us 20 20 100.00
burst_write 20 20 100.00
kmac_burst_write 1374.200s 156428.247us 20 20 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 53.960s 7038.516us 5 5 100.00
kmac_test_vectors_sha3_256 2621.080s 102247.258us 5 5 100.00
kmac_test_vectors_sha3_384 1763.530s 80544.208us 5 5 100.00
kmac_test_vectors_sha3_512 1402.650s 55433.581us 5 5 100.00
kmac_test_vectors_shake_128 3255.170s 218231.041us 5 5 100.00
kmac_test_vectors_shake_256 2863.460s 423358.980us 5 5 100.00
kmac_test_vectors_kmac 2.960s 52.919us 5 5 100.00
kmac_test_vectors_kmac_xof 3.720s 218.072us 5 5 100.00
sideload 20 20 100.00
kmac_sideload 439.710s 42735.316us 20 20 100.00
app 25 25 100.00
kmac_app 318.220s 106718.474us 25 25 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 311.350s 86541.198us 10 10 100.00
entropy_refresh 20 20 100.00
kmac_entropy_refresh 361.510s 107295.023us 20 20 100.00
error 20 20 100.00
kmac_error 431.850s 45598.868us 20 20 100.00
key_error 20 20 100.00
kmac_key_error 13.970s 22695.243us 20 20 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 7.760s 1242.511us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 43.180s 2255.471us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 36.440s 1163.184us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 54.930s 8009.884us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 37.020s 4304.371us 50 50 100.00
stress_all 20 20 100.00
kmac_stress_all 2885.810s 103473.352us 20 20 100.00
intr_test 10 10 100.00
kmac_intr_test 1.130s 50.683us 10 10 100.00
alert_test 10 10 100.00
kmac_alert_test 1.150s 32.207us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
kmac_tl_errors 4.520s 178.022us 25 25 100.00
tl_d_illegal_access 25 25 100.00
kmac_tl_errors 4.520s 178.022us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
kmac_csr_hw_reset 1.020s 14.806us 1 1 100.00
kmac_csr_rw 1.480s 95.086us 5 5 100.00
kmac_csr_aliasing 3.340s 289.314us 1 1 100.00
kmac_same_csr_outstanding 3.180s 142.839us 5 5 100.00
tl_d_partial_access 12 12 100.00
kmac_csr_hw_reset 1.020s 14.806us 1 1 100.00
kmac_csr_rw 1.480s 95.086us 5 5 100.00
kmac_csr_aliasing 3.340s 289.314us 1 1 100.00
kmac_same_csr_outstanding 3.180s 142.839us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 3.250s 154.775us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 3.250s 154.775us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 3.250s 154.775us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 3.250s 154.775us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 4.870s 277.609us 20 20 100.00
tl_intg_err 30 30 100.00
kmac_sec_cm 88.370s 21371.184us 5 5 100.00
kmac_tl_intg_err 6.040s 561.518us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
kmac_tl_intg_err 6.040s 561.518us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 37.020s 4304.371us 50 50 100.00
sec_cm_sw_key_key_masking 20 20 100.00
kmac_smoke 72.860s 22118.912us 20 20 100.00
sec_cm_key_sideload 20 20 100.00
kmac_sideload 439.710s 42735.316us 20 20 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 3.250s 154.775us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 88.370s 21371.184us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 88.370s 21371.184us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 88.370s 21371.184us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 20 20 100.00
kmac_smoke 72.860s 22118.912us 20 20 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 37.020s 4304.371us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 88.370s 21371.184us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 268.550s 23493.429us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 20 20 100.00
kmac_smoke 72.860s 22118.912us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
kmac_stress_all_with_rand_reset 128.790s 4388.336us 6 10 60.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:858) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 4 test runs
kmac_stress_all_with_rand_reset 60052579468515170652590719407569106224647994758447476428365987980182230308852 205
UVM_INFO @ 5954353923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 59534746857379942641617477079592070790567818143002414323083452860720882096555 221
UVM_INFO @ 2231928819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 92960388689612065326624745567825593840435666365915491643490218583369707254782 341
UVM_INFO @ 15196326225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 92610802121565020336585602413965401188749192257758248112294021880434670175388 222
UVM_INFO @ 10795346466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---