Simulation Results: kmac/unmasked

 
30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.66 %
  • code
  • 92.22 %
  • assert
  • 98.65 %
  • func
  • 96.10 %
  • line
  • 97.66 %
  • branch
  • 95.95 %
  • cond
  • 94.77 %
  • toggle
  • 100.00 %
  • FSM
  • 72.73 %
Validation stages
V1
100.00%
V2
95.26%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
kmac_smoke 71.290s 51640.699us 20 20 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.470s 113.745us 1 1 100.00
csr_rw 5 5 100.00
kmac_csr_rw 1.500s 31.786us 5 5 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 18.900s 6654.456us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 4.870s 1078.738us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
kmac_csr_mem_rw_with_rand_reset 2.440s 112.272us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
kmac_csr_rw 1.500s 31.786us 5 5 100.00
kmac_csr_aliasing 4.870s 1078.738us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 1.020s 29.871us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.360s 147.093us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 20 20 100.00
kmac_long_msg_and_output 4167.260s 521684.166us 20 20 100.00
burst_write 20 20 100.00
kmac_burst_write 942.250s 389287.485us 20 20 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2736.800s 439527.403us 5 5 100.00
kmac_test_vectors_sha3_256 2093.110s 85515.212us 5 5 100.00
kmac_test_vectors_sha3_384 1669.840s 77904.275us 5 5 100.00
kmac_test_vectors_sha3_512 650.730s 21868.830us 5 5 100.00
kmac_test_vectors_shake_128 2834.040s 1741226.392us 5 5 100.00
kmac_test_vectors_shake_256 1566.140s 207106.353us 5 5 100.00
kmac_test_vectors_kmac 2.880s 104.109us 5 5 100.00
kmac_test_vectors_kmac_xof 2.580s 815.513us 5 5 100.00
sideload 20 20 100.00
kmac_sideload 421.460s 125396.115us 20 20 100.00
app 25 25 100.00
kmac_app 303.160s 18516.971us 25 25 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 246.020s 19203.110us 10 10 100.00
entropy_refresh 20 20 100.00
kmac_entropy_refresh 320.050s 81093.026us 20 20 100.00
error 20 20 100.00
kmac_error 375.720s 79123.837us 20 20 100.00
key_error 20 20 100.00
kmac_key_error 13.160s 1893.595us 20 20 100.00
sideload_invalid 30 50 60.00
kmac_sideload_invalid 105.090s 10036.945us 30 50 60.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 37.780s 9647.317us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 36.080s 9366.493us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 56.970s 24240.922us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 39.040s 3819.671us 50 50 100.00
stress_all 20 20 100.00
kmac_stress_all 2262.000s 345087.689us 20 20 100.00
intr_test 10 10 100.00
kmac_intr_test 1.200s 35.956us 10 10 100.00
alert_test 10 10 100.00
kmac_alert_test 1.150s 14.626us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
kmac_tl_errors 4.710s 169.866us 25 25 100.00
tl_d_illegal_access 25 25 100.00
kmac_tl_errors 4.710s 169.866us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
kmac_csr_hw_reset 1.470s 113.745us 1 1 100.00
kmac_csr_rw 1.500s 31.786us 5 5 100.00
kmac_csr_aliasing 4.870s 1078.738us 1 1 100.00
kmac_same_csr_outstanding 2.970s 116.362us 5 5 100.00
tl_d_partial_access 12 12 100.00
kmac_csr_hw_reset 1.470s 113.745us 1 1 100.00
kmac_csr_rw 1.500s 31.786us 5 5 100.00
kmac_csr_aliasing 4.870s 1078.738us 1 1 100.00
kmac_same_csr_outstanding 2.970s 116.362us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.610s 424.510us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.610s 424.510us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.610s 424.510us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.610s 424.510us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 6.350s 1305.872us 20 20 100.00
tl_intg_err 30 30 100.00
kmac_sec_cm 59.860s 14147.486us 5 5 100.00
kmac_tl_intg_err 5.890s 3487.747us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
kmac_tl_intg_err 5.890s 3487.747us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 39.040s 3819.671us 50 50 100.00
sec_cm_sw_key_key_masking 20 20 100.00
kmac_smoke 71.290s 51640.699us 20 20 100.00
sec_cm_key_sideload 20 20 100.00
kmac_sideload 421.460s 125396.115us 20 20 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.610s 424.510us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 59.860s 14147.486us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 59.860s 14147.486us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 59.860s 14147.486us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 20 20 100.00
kmac_smoke 71.290s 51640.699us 20 20 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 39.040s 3819.671us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 59.860s 14147.486us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 167.190s 14246.086us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 20 20 100.00
kmac_smoke 71.290s 51640.699us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
kmac_stress_all_with_rand_reset 175.800s 9683.536us 7 10 70.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) 5 test runs
kmac_sideload_invalid 93846221300715716656210459255254153334775679226665624624275242830513912806544 81
UVM_INFO @ 10160515147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 2371009327069801443759493255501927740256805303601605098058425197240662608376 81
UVM_INFO @ 10088336511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 66357929007154491977750504300050454357409304305239687312958897809060058480381 80
UVM_INFO @ 10074608637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 19338528652060979460647469965953137657147995213966732736228935802840218597134 81
UVM_INFO @ 10041786787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 59190801105983755020628797903265178533825552148645811292406357859374155121657 81
UVM_INFO @ 10021828461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
kmac_stress_all_with_rand_reset 2989669472373083690087966213164996187851773244158554634874209256359082903860 192
UVM_INFO @ 8037923734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 105507116675974078528670536333795865725208910516868073394600557092845402613032 191
UVM_INFO @ 1677815397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 35703929799552888166137485786800077435062081354622795438301254359219851907160 141
UVM_INFO @ 22121897703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) 3 test runs
kmac_sideload_invalid 78961112932509734852645363961691144692043732009589445996611945546565302876522 81
UVM_INFO @ 10176204259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 112688679534536786726174092875680414405818098618570414669814095989385725124149 82
UVM_INFO @ 10054348663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 114480388905506147807196489347768029373986335532644460396396211448942517668211 82
UVM_INFO @ 10036944611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 2 test runs
kmac_sideload_invalid 106447059255398009046869988010275338295922142394883452939100330791121108118921 78
UVM_INFO @ 10010091830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 82868996634664577551758720845409460912597656746254176203751539911314292599380 78
UVM_INFO @ 10034977157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) 2 test runs
kmac_sideload_invalid 87650400891477949931387995410927867993595901896847450943366549492749040667667 83
UVM_INFO @ 10051189042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 88262347101903562483457452145430965441620753021475570602094019051783780896354 82
UVM_INFO @ 10099402039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) 1 test run
kmac_sideload_invalid 67745643146484973949693287908257442813351237643199552093079417771147078734996 91
UVM_INFO @ 10904473361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) 1 test run
kmac_sideload_invalid 45310939560465069980709085900441063552590460730348233123004595441877750755315 79
UVM_INFO @ 10069536212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=28) 1 test run
kmac_sideload_invalid 68854667607671680736253551932945148002772104438910500985978214037499461465798 109
UVM_INFO @ 10204199823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) 1 test run
kmac_sideload_invalid 60574007631479772802315449449957555993063889826286853473911627283660185428585 96
UVM_INFO @ 10990445160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) 1 test run
kmac_sideload_invalid 81682979583956170897756370724846347002274516341760905363993238378212170885189 89
UVM_INFO @ 10848612699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) 1 test run
kmac_sideload_invalid 63382808439536656000503481702114459852288055236910415204061044869238031820989 84
UVM_INFO @ 10325162870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) 1 test run
kmac_sideload_invalid 109539630165304333505816179914463343826334177130808284273797822863957728219410 91
UVM_INFO @ 10092302197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) 1 test run
kmac_sideload_invalid 103484655412341548979520004391976548625948094766876110660787212231941438371117 100
UVM_INFO @ 10766594572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---