Simulation Results: lc_ctrl/volatile_unlock_disabled

 
30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.31 %
  • code
  • 93.58 %
  • assert
  • 96.54 %
  • func
  • 89.81 %
  • block
  • 96.75 %
  • line
  • 97.38 %
  • branch
  • 91.72 %
  • toggle
  • 89.97 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.53%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 6.000s 1559.870us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 26.000s 22.809us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 24.000s 15.238us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 26.000s 99.810us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 26.000s 26.165us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 26.000s 49.266us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 24.000s 15.238us 5 5 100.00
lc_ctrl_csr_aliasing 26.000s 26.165us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 6.000s 1113.340us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 14.000s 308.505us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 25.000s 21.754us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 6.000s 171.520us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 7.000s 279.040us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 34.000s 482.034us 20 20 100.00
security_escalation 138 140 98.57
lc_ctrl_state_failure 7.000s 279.040us 20 20 100.00
lc_ctrl_prog_failure 6.000s 171.520us 20 20 100.00
lc_ctrl_errors 34.000s 482.034us 20 20 100.00
lc_ctrl_security_escalation 13.000s 2190.001us 20 20 100.00
lc_ctrl_jtag_state_failure 51.000s 3098.717us 18 20 90.00
lc_ctrl_jtag_prog_failure 20.000s 2272.880us 20 20 100.00
lc_ctrl_jtag_errors 61.000s 3746.244us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 8.000s 1430.988us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.000s 4528.576us 20 20 100.00
lc_ctrl_jtag_prog_failure 20.000s 2272.880us 20 20 100.00
lc_ctrl_jtag_errors 61.000s 3746.244us 20 20 100.00
lc_ctrl_jtag_access 34.000s 638.163us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 26.000s 1429.318us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 15.000s 79.367us 10 10 100.00
lc_ctrl_jtag_csr_rw 5.000s 111.869us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 31.000s 13183.112us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 21.000s 618.177us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 45.078us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 6.000s 684.573us 10 10 100.00
lc_ctrl_jtag_alert_test 19.000s 60.277us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 34.000s 1908.224us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 37.961us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 208.000s 77426.374us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 26.000s 22.746us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 275.111us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 275.111us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 26.000s 22.809us 1 1 100.00
lc_ctrl_csr_rw 24.000s 15.238us 5 5 100.00
lc_ctrl_csr_aliasing 26.000s 26.165us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 52.398us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 26.000s 22.809us 1 1 100.00
lc_ctrl_csr_rw 24.000s 15.238us 5 5 100.00
lc_ctrl_csr_aliasing 26.000s 26.165us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 52.398us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 5.000s 640.090us 5 5 100.00
lc_ctrl_tl_intg_err 5.000s 113.659us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 5.000s 113.659us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 14.000s 308.505us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 279.040us 20 20 100.00
lc_ctrl_sec_cm 5.000s 640.090us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 279.040us 20 20 100.00
lc_ctrl_sec_cm 5.000s 640.090us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 279.040us 20 20 100.00
lc_ctrl_sec_cm 5.000s 640.090us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 279.040us 20 20 100.00
lc_ctrl_sec_cm 5.000s 640.090us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 279.040us 20 20 100.00
lc_ctrl_sec_cm 5.000s 640.090us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 279.040us 20 20 100.00
lc_ctrl_sec_cm 5.000s 640.090us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 279.040us 20 20 100.00
lc_ctrl_sec_cm 5.000s 640.090us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 7.000s 279.040us 20 20 100.00
lc_ctrl_sec_cm 5.000s 640.090us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 13.000s 2190.001us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 6.000s 1113.340us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.000s 4528.576us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.000s 402.484us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.000s 402.484us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 11.000s 891.505us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.000s 420.085us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.000s 420.085us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
lc_ctrl_stress_all_with_rand_reset 72.000s 14961.383us 7 10 70.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
lc_ctrl_stress_all_with_rand_reset 110901434233313234313262031971511666653340050273257650490637781873695527010372 4015
UVM_INFO @ 14961383264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 102606964882071095309918926988929259750631053951565930053362132223747307420214 2612
UVM_INFO @ 20380398000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 5004282831854051529881697861708597320348639174739926625888761144226855683385 2382
UVM_INFO @ 3161128214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_state_failure 26886837983188477848714156468849272003793673361642963029567080226861103629502 178
UVM_INFO @ 85155002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 97186292396470440601423687210326600772233535894833689413235978339193553576579 178
UVM_INFO @ 90148038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---