Simulation Results: lc_ctrl/volatile_unlock_enabled

 
30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.77 %
  • code
  • 94.52 %
  • assert
  • 96.97 %
  • func
  • 89.81 %
  • block
  • 97.16 %
  • line
  • 97.69 %
  • branch
  • 92.79 %
  • toggle
  • 89.99 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
99.77%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 5.000s 309.538us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 53.624us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 2.000s 31.588us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 732.401us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 51.560us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 25.341us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 2.000s 31.588us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 51.560us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 4.000s 623.710us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 19.000s 2880.024us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 2.000s 14.628us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.000s 83.898us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 10.000s 2471.084us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 12.000s 1375.651us 20 20 100.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 10.000s 2471.084us 20 20 100.00
lc_ctrl_prog_failure 4.000s 83.898us 20 20 100.00
lc_ctrl_errors 12.000s 1375.651us 20 20 100.00
lc_ctrl_security_escalation 12.000s 2572.321us 20 20 100.00
lc_ctrl_jtag_state_failure 78.000s 4502.647us 19 20 95.00
lc_ctrl_jtag_prog_failure 16.000s 698.312us 20 20 100.00
lc_ctrl_jtag_errors 66.000s 4779.566us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 11.000s 571.695us 20 20 100.00
lc_ctrl_jtag_state_post_trans 20.000s 1927.183us 20 20 100.00
lc_ctrl_jtag_prog_failure 16.000s 698.312us 20 20 100.00
lc_ctrl_jtag_errors 66.000s 4779.566us 20 20 100.00
lc_ctrl_jtag_access 31.000s 1633.378us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 22.000s 1196.858us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 5.000s 3086.637us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.000s 1760.379us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 34.000s 3165.745us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 18.000s 1237.771us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 183.000us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 148.735us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 159.831us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 11.000s 2212.793us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 42.240us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 253.000s 12982.620us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 3.000s 60.494us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.000s 558.718us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.000s 558.718us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 53.624us 1 1 100.00
lc_ctrl_csr_rw 2.000s 31.588us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 51.560us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 221.309us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 53.624us 1 1 100.00
lc_ctrl_csr_rw 2.000s 31.588us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 51.560us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 221.309us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 8.000s 1667.370us 5 5 100.00
lc_ctrl_tl_intg_err 4.000s 79.613us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.000s 79.613us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 19.000s 2880.024us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 2471.084us 20 20 100.00
lc_ctrl_sec_cm 8.000s 1667.370us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 2471.084us 20 20 100.00
lc_ctrl_sec_cm 8.000s 1667.370us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.000s 2471.084us 20 20 100.00
lc_ctrl_sec_cm 8.000s 1667.370us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.000s 2471.084us 20 20 100.00
lc_ctrl_sec_cm 8.000s 1667.370us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 2471.084us 20 20 100.00
lc_ctrl_sec_cm 8.000s 1667.370us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 2471.084us 20 20 100.00
lc_ctrl_sec_cm 8.000s 1667.370us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 2471.084us 20 20 100.00
lc_ctrl_sec_cm 8.000s 1667.370us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 10.000s 2471.084us 20 20 100.00
lc_ctrl_sec_cm 8.000s 1667.370us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 12.000s 2572.321us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 4.000s 623.710us 20 20 100.00
lc_ctrl_jtag_state_post_trans 20.000s 1927.183us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.000s 2885.033us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.000s 2885.033us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 9.000s 778.221us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.000s 3767.378us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.000s 3767.378us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
lc_ctrl_stress_all_with_rand_reset 56.000s 11357.497us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 53754767837674649271909982033369029002194224748481816802714637604027030284340 176
UVM_INFO @ 759848775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 6802982541956210901830559055181904764314095678129093832062427900724993930567 161
UVM_INFO @ 108945108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 17671961403238726135261433852015092244075162755808671139772570565638933883254 801
UVM_INFO @ 1124117396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 94005740099292337643481344119647061894436126649928780395633072431465608910146 797
UVM_INFO @ 5711105404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 25793076085732797824391841591737678588037690621974324740808397433601995511378 1920
UVM_INFO @ 11357496612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_failure 83120773444527119575722879243009731921024676908145518576127691406180048081565 177
UVM_INFO @ 192342973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---