Simulation Results: otbn

 
30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.96 %
  • code
  • 96.62 %
  • assert
  • 91.27 %
  • func
  • 100.00 %
  • block
  • 99.49 %
  • line
  • 99.62 %
  • branch
  • 93.43 %
  • toggle
  • 93.45 %
  • FSM
  • 100.00 %
Validation stages
V1
99.14%
V2
97.55%
V2S
98.18%
V3
40.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 151.524us 1 1 100.00
single_binary 99 100 99.00
otbn_single 133.000s 629.098us 99 100 99.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 7.000s 43.136us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 7.000s 39.591us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 10.000s 84.336us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 8.000s 40.354us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 10.000s 63.404us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 7.000s 39.591us 5 5 100.00
otbn_csr_aliasing 8.000s 40.354us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 150.000s 23896.811us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 45.000s 5057.995us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 67.000s 266.981us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 55.000s 335.877us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 100.000s 201.842us 10 10 100.00
stress_all 9 10 90.00
otbn_stress_all 245.000s 824.609us 9 10 90.00
lc_escalation 58 60 96.67
otbn_escalate 24.000s 90.314us 58 60 96.67
zero_state_err_urnd 4 5 80.00
otbn_zero_state_err_urnd 9.000s 54.504us 4 5 80.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 12.000s 150.304us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 8.000s 33.813us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 6.000s 14.945us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 8.000s 153.320us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 8.000s 153.320us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 7.000s 43.136us 1 1 100.00
otbn_csr_rw 7.000s 39.591us 5 5 100.00
otbn_csr_aliasing 8.000s 40.354us 1 1 100.00
otbn_same_csr_outstanding 6.000s 54.307us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 7.000s 43.136us 1 1 100.00
otbn_csr_rw 7.000s 39.591us 5 5 100.00
otbn_csr_aliasing 8.000s 40.354us 1 1 100.00
otbn_same_csr_outstanding 6.000s 54.307us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 15.000s 55.326us 10 10 100.00
otbn_dmem_err 17.000s 34.186us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 21.000s 285.446us 5 5 100.00
otbn_controller_ispr_rdata_err 11.000s 37.206us 5 5 100.00
otbn_mac_bignum_acc_err 12.000s 59.834us 5 5 100.00
otbn_urnd_err 9.000s 18.888us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 7.000s 38.127us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 9.000s 20.879us 2 2 100.00
otbn_non_sec_partial_wipe 8 10 80.00
otbn_partial_wipe 6.000s 10.544us 8 10 80.00
tl_intg_err 30 30 100.00
otbn_sec_cm 303.000s 1373.961us 5 5 100.00
otbn_tl_intg_err 44.000s 262.057us 25 25 100.00
passthru_mem_tl_intg_err 5 5 100.00
otbn_passthru_mem_tl_intg_err 69.000s 476.721us 5 5 100.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 303.000s 1373.961us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 303.000s 1373.961us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 151.524us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 17.000s 34.186us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 15.000s 55.326us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 44.000s 262.057us 25 25 100.00
sec_cm_controller_fsm_global_esc 58 60 96.67
otbn_escalate 24.000s 90.314us 58 60 96.67
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 15.000s 55.326us 10 10 100.00
otbn_dmem_err 17.000s 34.186us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 54.504us 4 5 80.00
otbn_illegal_mem_acc 7.000s 38.127us 5 5 100.00
otbn_sec_cm 303.000s 1373.961us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 303.000s 1373.961us 5 5 100.00
sec_cm_scramble_key_sideload 99 100 99.00
otbn_single 133.000s 629.098us 99 100 99.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 15.000s 55.326us 10 10 100.00
otbn_dmem_err 17.000s 34.186us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 54.504us 4 5 80.00
otbn_illegal_mem_acc 7.000s 38.127us 5 5 100.00
otbn_sec_cm 303.000s 1373.961us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 303.000s 1373.961us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 58 60 96.67
otbn_escalate 24.000s 90.314us 58 60 96.67
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 15.000s 55.326us 10 10 100.00
otbn_dmem_err 17.000s 34.186us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 54.504us 4 5 80.00
otbn_illegal_mem_acc 7.000s 38.127us 5 5 100.00
otbn_sec_cm 303.000s 1373.961us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 303.000s 1373.961us 5 5 100.00
sec_cm_data_reg_sw_sca 99 100 99.00
otbn_single 133.000s 629.098us 99 100 99.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 9.000s 36.728us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 9.000s 31.615us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 55.000s 826.556us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 55.000s 826.556us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 18.000s 64.159us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 303.000s 1373.961us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 303.000s 1373.961us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 11.000s 63.902us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 303.000s 1373.961us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 303.000s 1373.961us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 19.000s 39.844us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 19.000s 39.844us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 19.000s 36.806us 7 7 100.00
sec_cm_data_mem_sec_wipe 99 100 99.00
otbn_single 133.000s 629.098us 99 100 99.00
sec_cm_instruction_mem_sec_wipe 99 100 99.00
otbn_single 133.000s 629.098us 99 100 99.00
sec_cm_data_reg_sw_sec_wipe 99 100 99.00
otbn_single 133.000s 629.098us 99 100 99.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 100.000s 201.842us 10 10 100.00
sec_cm_ctrl_flow_count 99 100 99.00
otbn_single 133.000s 629.098us 99 100 99.00
sec_cm_ctrl_flow_sca 99 100 99.00
otbn_single 133.000s 629.098us 99 100 99.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 18.000s 145.467us 5 5 100.00
sec_cm_key_sideload 99 100 99.00
otbn_single 133.000s 629.098us 99 100 99.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 303.000s 1373.961us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
otbn_stress_all_with_rand_reset 386.000s 3401.903us 4 10 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 9.000s 28.483us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
otbn_stress_all_with_rand_reset 81521573744285828541927910304955062521928498483965548286853781652766088125708 171
UVM_INFO @ 409800477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 83723312429015948570938589895901599101625119082145438592295586426616747560245 327
UVM_INFO @ 7922755219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 104008750086271245489072422565739064090186342075828092837246272954148004957681 195
UVM_INFO @ 754881862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 99422475659655633625276294421986393693484562877978830084235820210990949386374 154
UVM_INFO @ 131621827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 12006974628268097431971147308156531201155525029462183273826354950212055757995 151
UVM_INFO @ 233720415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 3939243897977277710031348323651247401009354821388962272082210821545041691936 169
UVM_INFO @ 909446997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 2 test runs
otbn_zero_state_err_urnd 98767154058569829147078212544327138336877687519018794630559765852144834540013 110
UVM_ERROR @ 40323987 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 40323987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 46304841386593395091971844774061175084370254810119184558595488071795767025197 115
UVM_ERROR @ 13337694 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 13337694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 2 test runs
otbn_partial_wipe 115655112402654501175849947539743025037019863913158326955556064515321780895469 107
UVM_INFO @ 17023813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all 101335830444995600513590520394414402301136806583475414010714799334500039667964 175
UVM_INFO @ 317025096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_escalate 43443594977174296548930274521764119467375857011533627675020272960699348836566 108
UVM_INFO @ 3941768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,161): Assertion IdleIfLockedAndNotRotatingKeys_A has failed (* cycles, starting * PS) 1 test run
otbn_partial_wipe 83374303454381314448100687870636814972625581600583909815900789249372114909460 119
UVM_ERROR @ 18789168 ps: (otbn_idle_checker.sv:161) [ASSERT FAILED] IdleIfLockedAndNotRotatingKeys_A
UVM_INFO @ 18789168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_single 109321684802527925349963096154899394783190727221861291145537982568458120370609 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1