Simulation Results

Simulation Results: otp_ctrl

30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.40 %

code
80.76 %

assert
94.93 %

func
80.52 %

line
88.39 %

branch
86.46 %

cond
88.49 %

toggle
88.27 %

FSM
52.19 %

Validation stages

V1		84.62%
V2		70.73%
V2S		70.61%
V3		7.92%

22/26 passed

84.62 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wake_up				1	1	100.00
	otp_ctrl_wake_up	1.870s	66.646us	1	1	100.00
smoke				8	10	80.00
	otp_ctrl_smoke	13.160s	4311.648us	8	10	80.00
csr_hw_reset				1	1	100.00
	otp_ctrl_csr_hw_reset	3.900s	1683.286us	1	1	100.00
csr_rw				5	5	100.00
	otp_ctrl_csr_rw	2.920s	208.494us	5	5	100.00
csr_bit_bash				1	1	100.00
	otp_ctrl_csr_bit_bash	5.320s	622.768us	1	1	100.00
csr_aliasing				1	1	100.00
	otp_ctrl_csr_aliasing	10.320s	380.208us	1	1	100.00
csr_mem_rw_with_rand_reset				3	5	60.00
	otp_ctrl_csr_mem_rw_with_rand_reset	4.940s	1954.039us	3	5	60.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	otp_ctrl_csr_rw	2.920s	208.494us	5	5	100.00
	otp_ctrl_csr_aliasing	10.320s	380.208us	1	1	100.00
mem_walk				1	1	100.00
	otp_ctrl_mem_walk	1.770s	151.453us	1	1	100.00
mem_partial_access				1	1	100.00
	otp_ctrl_mem_partial_access	2.410s	156.222us	1	1	100.00

522/738 passed

70.73 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
dai_access_partition_walk				0	1	0.00
	otp_ctrl_partition_walk	132.520s	6596.586us	0	1	0.00
init_fail				193	300	64.33
	otp_ctrl_init_fail	8.940s	2594.657us	193	300	64.33
partition_check				23	60	38.33
	otp_ctrl_background_chks	36.970s	4976.072us	5	10	50.00
	otp_ctrl_check_fail	47.650s	27806.199us	18	50	36.00
regwen_during_otp_init				20	30	66.67
	otp_ctrl_regwen	9.840s	1084.041us	20	30	66.67
partition_lock				13	30	43.33
	otp_ctrl_dai_lock	72.660s	30520.976us	13	30	43.33
interface_key_check				5	10	50.00
	otp_ctrl_parallel_key_req	34.420s	6232.579us	5	10	50.00
lc_interactions				190	210	90.48
	otp_ctrl_parallel_lc_req	18.910s	1486.469us	7	10	70.00
	otp_ctrl_parallel_lc_esc	58.540s	35519.705us	183	200	91.50
otp_dai_errors				10	10	100.00
	otp_ctrl_dai_errs	64.730s	3063.865us	10	10	100.00
otp_macro_errors				3	10	30.00
	otp_ctrl_macro_errs	57.340s	4553.849us	3	10	30.00
test_access				7	10	70.00
	otp_ctrl_test_access	28.560s	1747.419us	7	10	70.00
stress_all				1	10	10.00
	otp_ctrl_stress_all	179.420s	133498.298us	1	10	10.00
intr_test				10	10	100.00
	otp_ctrl_intr_test	2.670s	156.878us	10	10	100.00
alert_test				10	10	100.00
	otp_ctrl_alert_test	3.500s	1082.128us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	otp_ctrl_tl_errors	9.150s	2959.978us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	otp_ctrl_tl_errors	9.150s	2959.978us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	otp_ctrl_csr_hw_reset	3.900s	1683.286us	1	1	100.00
	otp_ctrl_csr_rw	2.920s	208.494us	5	5	100.00
	otp_ctrl_csr_aliasing	10.320s	380.208us	1	1	100.00
	otp_ctrl_same_csr_outstanding	4.190s	2350.196us	5	5	100.00
tl_d_partial_access				12	12	100.00
	otp_ctrl_csr_hw_reset	3.900s	1683.286us	1	1	100.00
	otp_ctrl_csr_rw	2.920s	208.494us	5	5	100.00
	otp_ctrl_csr_aliasing	10.320s	380.208us	1	1	100.00
	otp_ctrl_same_csr_outstanding	4.190s	2350.196us	5	5	100.00

V2S

466/660 passed

70.61 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
tl_intg_err				28	30	93.33
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
	otp_ctrl_tl_intg_err	38.980s	24028.006us	25	25	100.00
prim_count_check				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
prim_fsm_check				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_bus_integrity				25	25	100.00
	otp_ctrl_tl_intg_err	38.980s	24028.006us	25	25	100.00
sec_cm_secret_mem_scramble				8	10	80.00
	otp_ctrl_smoke	13.160s	4311.648us	8	10	80.00
sec_cm_part_mem_digest				8	10	80.00
	otp_ctrl_smoke	13.160s	4311.648us	8	10	80.00
sec_cm_dai_fsm_sparse				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_kdi_fsm_sparse				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_lci_fsm_sparse				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_part_fsm_sparse				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_scrmbl_fsm_sparse				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_timer_fsm_sparse				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_dai_ctr_redun				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_kdi_seed_ctr_redun				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_kdi_entropy_ctr_redun				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_lci_ctr_redun				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_part_ctr_redun				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_scrmbl_ctr_redun				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_timer_integ_ctr_redun				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_timer_cnsty_ctr_redun				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_timer_lfsr_redun				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_dai_fsm_local_esc				186	205	90.73
	otp_ctrl_parallel_lc_esc	58.540s	35519.705us	183	200	91.50
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_lci_fsm_local_esc				183	200	91.50
	otp_ctrl_parallel_lc_esc	58.540s	35519.705us	183	200	91.50
sec_cm_kdi_fsm_local_esc				183	200	91.50
	otp_ctrl_parallel_lc_esc	58.540s	35519.705us	183	200	91.50
sec_cm_part_fsm_local_esc				186	210	88.57
	otp_ctrl_parallel_lc_esc	58.540s	35519.705us	183	200	91.50
	otp_ctrl_macro_errs	57.340s	4553.849us	3	10	30.00
sec_cm_scrmbl_fsm_local_esc				183	200	91.50
	otp_ctrl_parallel_lc_esc	58.540s	35519.705us	183	200	91.50
sec_cm_timer_fsm_local_esc				186	205	90.73
	otp_ctrl_parallel_lc_esc	58.540s	35519.705us	183	200	91.50
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_dai_fsm_global_esc				186	205	90.73
	otp_ctrl_parallel_lc_esc	58.540s	35519.705us	183	200	91.50
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_lci_fsm_global_esc				183	200	91.50
	otp_ctrl_parallel_lc_esc	58.540s	35519.705us	183	200	91.50
sec_cm_kdi_fsm_global_esc				183	200	91.50
	otp_ctrl_parallel_lc_esc	58.540s	35519.705us	183	200	91.50
sec_cm_part_fsm_global_esc				186	210	88.57
	otp_ctrl_parallel_lc_esc	58.540s	35519.705us	183	200	91.50
	otp_ctrl_macro_errs	57.340s	4553.849us	3	10	30.00
sec_cm_scrmbl_fsm_global_esc				183	200	91.50
	otp_ctrl_parallel_lc_esc	58.540s	35519.705us	183	200	91.50
sec_cm_timer_fsm_global_esc				186	205	90.73
	otp_ctrl_parallel_lc_esc	58.540s	35519.705us	183	200	91.50
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_part_data_reg_integrity				193	300	64.33
	otp_ctrl_init_fail	8.940s	2594.657us	193	300	64.33
sec_cm_part_data_reg_bkgn_chk				18	50	36.00
	otp_ctrl_check_fail	47.650s	27806.199us	18	50	36.00
sec_cm_part_mem_regren				13	30	43.33
	otp_ctrl_dai_lock	72.660s	30520.976us	13	30	43.33
sec_cm_part_mem_sw_unreadable				13	30	43.33
	otp_ctrl_dai_lock	72.660s	30520.976us	13	30	43.33
sec_cm_part_mem_sw_unwritable				13	30	43.33
	otp_ctrl_dai_lock	72.660s	30520.976us	13	30	43.33
sec_cm_lc_part_mem_sw_noaccess				13	30	43.33
	otp_ctrl_dai_lock	72.660s	30520.976us	13	30	43.33
sec_cm_access_ctrl_mubi				13	30	43.33
	otp_ctrl_dai_lock	72.660s	30520.976us	13	30	43.33
sec_cm_token_valid_ctrl_mubi				8	10	80.00
	otp_ctrl_smoke	13.160s	4311.648us	8	10	80.00
sec_cm_lc_ctrl_intersig_mubi				13	30	43.33
	otp_ctrl_dai_lock	72.660s	30520.976us	13	30	43.33
sec_cm_test_bus_lc_gated				8	10	80.00
	otp_ctrl_smoke	13.160s	4311.648us	8	10	80.00
sec_cm_test_tl_lc_gate_fsm_sparse				3	5	60.00
	otp_ctrl_sec_cm	403.560s	72821.642us	3	5	60.00
sec_cm_direct_access_config_regwen				20	30	66.67
	otp_ctrl_regwen	9.840s	1084.041us	20	30	66.67
sec_cm_check_trigger_config_regwen				8	10	80.00
	otp_ctrl_smoke	13.160s	4311.648us	8	10	80.00
sec_cm_check_config_regwen				8	10	80.00
	otp_ctrl_smoke	13.160s	4311.648us	8	10	80.00
sec_cm_macro_mem_integrity				3	10	30.00
	otp_ctrl_macro_errs	57.340s	4553.849us	3	10	30.00

8/101 passed

7.92 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
otp_ctrl_low_freq_read				0	1	0.00
	otp_ctrl_low_freq_read	140.590s	59304.263us	0	1	0.00
stress_all_with_rand_reset				8	100	8.00
	otp_ctrl_stress_all_with_rand_reset	146.790s	23275.011us	8	100	8.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value:				118 test runs
	otp_ctrl_init_fail	26798734080531931762180165894079513178600502705145971531128181695582097311061	233	UVM_INFO @ 45862626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	107399491592969618786346903586131199333778954573517462591337633985856504920219	2192	UVM_INFO @ 71826786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	106845278236774715148961527275704661498114826090494980122846647155525266690347	5014	UVM_INFO @ 169656593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_smoke	113152443974500485696814817212585477247154010753593685533925375838110363542465	5756	UVM_INFO @ 421694993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	26746229185222634533659517666011117942082825691594671000747516126991692700304	99	UVM_INFO @ 87640011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	53890335030791033236132478522353474551113216951359234433633342164399354269381	560	UVM_INFO @ 247522142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_smoke	65103590227244642327838861810310949078981484418205011967376197354395906673016	3044	UVM_INFO @ 170599835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	74657047788723217175717803526226587561135809574798828664627159829167937299108	1551	UVM_INFO @ 213389060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	21594957680991328545281200374566475089921109365394749368124442021625087300024	5386	UVM_INFO @ 1725433024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	67831049524993617170575582867366760149615033176985743049903230305318686104139	2227	UVM_INFO @ 74726003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	104485240430488208741423770237625109411625613832311887258191768538235089633318	1838	UVM_INFO @ 152961807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	9270467084945919720744578226451150501664690591091407051188447709175058898925	414	UVM_INFO @ 364988846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	104595727432372938527654555502964140186430281658705301680689156039442489377689	5800	UVM_INFO @ 358124683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	41339512246473966128920881212838010956615978976338493759472631882257389878203	1511	UVM_INFO @ 250055976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	54182542049291893691582090816722010952026611974263339409925624112858853200192	2294	UVM_INFO @ 120457331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	37561547466121455278281244830098556053869515409443136905064604435716566172422	1460	UVM_INFO @ 1233129315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	106959035328258646278438740646850742885580539673475744478517616960681959124601	1695	UVM_INFO @ 950187476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	78149021469819137938725261922600970817842725578286221835173620282420530795905	3247	UVM_INFO @ 295899856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	57753801831055570312402149393523332979766135396290258456674611298743423025879	321	UVM_INFO @ 43659778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	13319348157928458558370218646236864858080476707998055002931654763303000475419	4864	UVM_INFO @ 241406919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	60698860887527260814598418511572501838815598781586539023805812863110590116248	887	UVM_INFO @ 84390425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	98532081584747926078470016703548726142464581201790126211340089239153895698661	915	UVM_INFO @ 162327638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	42908226988437921382221310216994778544995416753818866960169933073861207093276	1317	UVM_INFO @ 54653468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	2023128213998179836506942013214598554650319986942781635920646797646620988593	231	UVM_INFO @ 174780351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	29758010956475221779827102852893242597940141300454098562151790683340419854680	1071	UVM_INFO @ 57120958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	77276842971456246594448689305253712157860804456159133869110381552610188871320	2693	UVM_INFO @ 131158424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	54578144092423794042080269005689983985538769871861059941280428748437313641336	323	UVM_INFO @ 216083650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	35307939738230385375717373783333098282884065376440047635647207258982765717777	439	UVM_INFO @ 137599229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	56694949327272616883875174679929650378075568233592864463261768876398690594694	1089	UVM_INFO @ 78586034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	6939695039948756206468679211816292947736199558869064038814517025948752454941	267	UVM_INFO @ 37330605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	89639283332430222046749210319395424544065114696444360926234678561225046724651	307	UVM_INFO @ 39345138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	38545231524864610769494217270341133753916594469791043414665471859706653943993	2359	UVM_INFO @ 1225978641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	67381485604884632149405668699972554504604961986801141183777939158069164195959	715	UVM_INFO @ 66859456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	31297184619419413158961673940090108547575847417999123674228183857933173666649	1899	UVM_INFO @ 155752722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	8758042652370360497537162239034519588820461457404432521701471964949958664625	99	UVM_INFO @ 499937534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	90142000208645171961901230106980496400222421108942740310393316983535507369541	491	UVM_INFO @ 116759539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	62883986159868313174487366162619318159238111297626853428696074846661362057655	517	UVM_INFO @ 1050743083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	111370867126609362544717722582027566774991524150494647791157122694370716481333	1281	UVM_INFO @ 160564901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	93397296436956866532688495355042102843946099960421759118277192477316022511456	1953	UVM_INFO @ 65357397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	12563711957345068394282516700687451850987278519495940571867534736510735796444	367	UVM_INFO @ 38622512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	89051337930173530776569303964451270309071403017794758119448384253453905883996	1887	UVM_INFO @ 908164411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	64314238567190193997805237113009779168246723791399544734629044427658008419303	655	UVM_INFO @ 40063825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	24737038112521741889197769447651587502589650768165111037016169743229107848080	1287	UVM_INFO @ 53616817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	107680807482848241972450505707813470009188531622256592062600216615739063076690	183	UVM_INFO @ 101470850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	48943539321812850686417063200398898373069009200827862360985316026526818121282	805	UVM_INFO @ 40938700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	71069240469537817845571343053958937789564867784625173849198268845353840658710	215	UVM_INFO @ 129666284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	33746354148599322968729991240943976040489554072474102268704229993972915221378	1087	UVM_INFO @ 727578713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	50813182797608037846665814603961578974930545468424594132904395532630875981360	553	UVM_INFO @ 45987007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	73743324507790784341836234910840459506103196109365054689777176936473558150436	1099	UVM_INFO @ 50541146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	81793075843449870300254626429716496604474727722918623004367159241867191404441	183	UVM_INFO @ 33401309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	38413918085218630725510124658231597466828286325267176078349177076330198990803	1535	UVM_INFO @ 54573273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	103866570535959415956858807459836864317621068612802858472816795185714275943002	1529	UVM_INFO @ 172484285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	110629143286177647771466826742588042196753873952182151648221060898505796976180	421	UVM_INFO @ 82045022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	35185274233584437637663837773070088480781153033257290668515564203214035988	145	UVM_INFO @ 74404564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	46285144155847057097952125747708891112093690848153196891936632052404265746420	459	UVM_INFO @ 593891365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	105141229103547660385318765252815922090959998067798926530009890926558776788973	1547	UVM_INFO @ 1001148830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	16107664070573808305026688842716961353736242923487566380422252825048824369463	241	UVM_INFO @ 46194180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	55793535686601470417979386338537071347383137812537044986032485616663909692923	267	UVM_INFO @ 748464666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	86745394385987735872971873976872986187394444738555478540451684258852990352446	1075	UVM_INFO @ 180870727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	13636119581023392687453573052931830499232043569132983379646404019161716459659	2743	UVM_INFO @ 290327072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	96446016107709762845613859308047524662869910787038062163260120176268837747842	145	UVM_INFO @ 58525144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	84050789202164762593123465461440368506380276163043333565366452136094507864733	981	UVM_INFO @ 47152508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	16991428875603460493925345796077415493318581657603186552574731288604098627069	99	UVM_INFO @ 69353299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	29785499033521177118096177972895233742592240593428397100061030169235668390651	563	UVM_INFO @ 39133719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	62123295948843104717397847303421347502381180928353124631917411841715413537380	455	UVM_INFO @ 614120019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	19929847839498778365975287674172364702752828982586357989829063926936929906059	481	UVM_INFO @ 43651966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	96993363745973617287616191464203950711969537633357440373280812195794190002899	99	UVM_INFO @ 61917090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	15660774769308807581844767588446111748693168755712173707411861535697257826972	553	UVM_INFO @ 145800366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	80256677089863219381985354304654931312186284337086298838947659452765342344623	971	UVM_INFO @ 86098212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	41654927030523289256633850868499529193478225373418035820242082647040223018653	99	UVM_INFO @ 693516309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	62449935752676023318788613198855860945213975454465484610760273417605812483886	345	UVM_INFO @ 68341988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	11674100788484177151433933769626101684924260311438612947831686270942280749364	801	UVM_INFO @ 223826509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	29988448382901838792778099947757365965995490064710524812541300889887938626677	361	UVM_INFO @ 70544443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	66382845759148751667997234306766426605336719650573308718582059685082961319609	779	UVM_INFO @ 53536788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	70015244619562066203745408282604449379041124179704253116322983804511062977027	777	UVM_INFO @ 58311600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	34696727042911513520014188637540834556511701962979654043420070815388148538580	395	UVM_INFO @ 35893038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	112119432003646917905951527337317825081915708614250132425081655272491518114895	1097	UVM_INFO @ 280658694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	110177942245671669634653681985790666553807090397443601347204161343649074827235	813	UVM_INFO @ 671725929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	64926284449167064594096569704603795613476460724755613568676127789905744758902	655	UVM_INFO @ 168448767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	77127507883628915665514395817334504044751473081510235018283607036406240649035	1437	UVM_INFO @ 803456276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	101681219500151747742942711614709950138058034024866912859549899896637359898259	467	UVM_INFO @ 131227295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	50740049512519216270440740867022520739238668613502940263463958524711537214613	3091	UVM_INFO @ 1197897235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	89172103101476807272930857359211321208477758726110386195349338659667445049306	1067	UVM_INFO @ 67717048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	109513722017737858305549336069798328820584670837751594269485010521203146560501	99	UVM_INFO @ 615805652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	79754750961324926170600434098839790763246534455059797801355812238147901804075	141	UVM_INFO @ 638984426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	41279262520236895324578869886310607060329652583217809666392941625317467980226	1559	UVM_INFO @ 219227848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	59493657964761153061361567782760110134935061551711915627806978191593640719172	769	UVM_INFO @ 48603147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	67797469020759734095810629096068219248063471170689241046634166201740281609114	727	UVM_INFO @ 655635460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	64527509460591305683132380308643234290318665490544668046370722298037053524518	99	UVM_INFO @ 83997806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	96455356039709809130483424948000656352985615587327480529564507467789849189560	1507	UVM_INFO @ 822008886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	105320652405645503298426506679587738080179983189077081143604800911618057705426	2185	UVM_INFO @ 130515831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	68466050319346699515317725090364851413707906903606996774595798669079863328416	2339	UVM_INFO @ 83717832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	52211981322566642667045962935522585814185391299508513142831377383723382788200	507	UVM_INFO @ 114047565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	74352639697347857029121268870042728119425773090733027229822009471721986653666	181	UVM_INFO @ 35689807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	31032190819417843914562404897892166411944831220973951346913722664998874071084	593	UVM_INFO @ 53171467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	9331461116743591177981788311478108313702031232480980216580199104683176639591	689	UVM_INFO @ 945506580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	75729579773351697403474769561411246034895340188960766767178739064521249307429	1717	UVM_INFO @ 53124549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	79026327376229193389309334517823341252955475347786050675862731667931848845468	543	UVM_INFO @ 267482683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	83982567282004379847984590041725330182380788295823028056618170515716023691227	1327	UVM_INFO @ 142951260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	98138675739320990624451829974533372475178269567665415193734527801348815295049	549	UVM_INFO @ 153529937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	33590800031137567704136393085880786070377302945728320333859781017662119992233	723	UVM_INFO @ 689594384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	56881642238645745997120908481592873883425613176129709019698537541535167128524	989	UVM_INFO @ 42868621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	108681767286113862127053319507459560662094061637582635290599991085472491892558	583	UVM_INFO @ 147885726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	80557413068635894529937247659541177663223498295748220726554375366559646566110	1647	UVM_INFO @ 863071171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	26255518387444642787841536111023480902630377235287761693310833460595261905572	139	UVM_INFO @ 127170322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	34388358275786625266087440051398302045619840033443420073194738198351125712603	2637	UVM_INFO @ 1098147734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	105644226073343135953963840441435426457904088162485170929528155037952880444669	99	UVM_INFO @ 833864990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	61594874060113844004717534741953505424763824431965690382412883799471773907347	497	UVM_INFO @ 836041925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	2275396788548252279690123937743484990877873694099737791708587888450306139573	141	UVM_INFO @ 526900115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	58192460197713781918089483163083549046990394045145410231269376135827619325007	669	UVM_INFO @ 156998088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	89431996698228291524624176608913164495881991591660103427612831269340408253377	99	UVM_INFO @ 30948585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	31414240073396861539227745747807373391783505476677695063932635389940286734854	567	UVM_INFO @ 38988147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	20374107399665146822313716889817078062000305025064959651272765113288268021575	283	UVM_INFO @ 44470825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	21669262422295532307421231707838293760816545334079107952524535814866461580928	449	UVM_INFO @ 35604024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	92684363045163581850094712896335380335403476875424872773322883635314813407094	741	UVM_INFO @ 856386085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	23452775897168983551516540551610971453285493407106850128280376819849549054862	99	UVM_INFO @ 44663435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	12362502159896886969927484165973382819475025657689162487028190397841633983711	953	UVM_INFO @ 1091190488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	6250233011427336952975084679722042700400239592788611227277173549694430411445	505	UVM_INFO @ 76098613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs []) reg name: otp_ctrl_core_reg_block.err_code_				69 test runs
	otp_ctrl_check_fail	80961638858874144567322461823187832826876669553493326734455877158190648901533	3406	UVM_INFO @ 538080649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	73907061979023315121375110737824087499091917969083671264411317920191236300487	2724	UVM_INFO @ 628588360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_background_chks	67366950631182485383233516311198891963583408546383229157948428365282705009403	716	UVM_INFO @ 88824164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	83846743699050461364577861688081189514145516805084315887790994089113560190435	6311	UVM_INFO @ 436601404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	14384047626832542399049684180711692217478668616378795653197546153409589393124	3505	UVM_INFO @ 586863959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_key_req	108774438099741745035617002764053049746981892404285265621817964272419727396620	6517	UVM_INFO @ 537371072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	35467339422033639923870021953964059304110786379847221626551434175871052628167	2395	UVM_INFO @ 1168117329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	18987973220458887459104966570813939031851421620983103842034104225276056662985	1449	UVM_INFO @ 492768619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	28959584265241012535933661224346436481913333290457935190943240156118922899922	1431	UVM_INFO @ 200660362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_test_access	52199958934457200773251972964787718410576940761656958528822853857735321396966	4296	UVM_INFO @ 162463315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	84999824883414726061958052609467835600070004800673643058684423185307318607827	9222	UVM_INFO @ 4714545400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	31226517243971369421811748231972072056459254552430071107298642814841397474133	540	UVM_INFO @ 277928109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	37039901671667941134371486919872350644362985597763310211068182721904367423789	12373	UVM_INFO @ 3487264693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	113117962405190049406511197487700787475405400290440254065716760009092202122832	3355	UVM_INFO @ 338858312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_background_chks	47721144007637673415105643371843292090524433303126437763406166095063197474901	3622	UVM_INFO @ 4155754523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	6603504960161782813571655608607719139185142152593005589496121961315426467285	5624	UVM_INFO @ 1715861248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	66879830901924912990528808935633504008131905739815772216013005837944187741209	870	UVM_INFO @ 162598205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	112199223494042467501742948292865184175965126943506434791465974384926102030973	9082	UVM_INFO @ 5944516685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	111390123010030573404174383510612620708395780773844916053283373295097701541218	3539	UVM_INFO @ 1672351366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_test_access	79886756819604461971914473053075828270795614442527149097559914556684749429195	1827	UVM_INFO @ 136227493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	93594675088047461563432796814522238750196669991863488946033384648220893070540	582	UVM_INFO @ 886227231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_key_req	76911811097388882964793047175197895122982630544076262581891671391657961093905	4004	UVM_INFO @ 241890903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	109649033717591359430679516034088700037396200233002411314430063989544908937302	160	UVM_INFO @ 36353682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	7979215582116125703968325740626290245106728463513220105582723808386547293313	47245	UVM_INFO @ 1581650778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	104806329368908150264757327634110989423729107042183615726294856140092906372666	2472	UVM_INFO @ 723920329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	111386276734191448463085828984155466163893488032380354612101267080310971058801	992	UVM_INFO @ 116011903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	55622931467503682018825332621863651738051932123096628243575070881685735499251	1134	UVM_INFO @ 110284856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	88295613237040131813492710209663037392677403634222965433728633198754474989510	4537	UVM_INFO @ 623399594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	89279411851940881447686091490289657129184907875020330458852119269199306619184	5726	UVM_INFO @ 4778584175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	78210599212070622185955319192746743738676013367574794674871450466522159149740	13786	UVM_INFO @ 2277185803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	6646945432147868392003257433378838328902543785150808954781935700273136205264	4932	UVM_INFO @ 1933099026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	23406167581046900708718415851696159697548874032110586841961267288030523616507	988	UVM_INFO @ 66601035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	36641682207006878733221545996718260422120142540384151255458115250923439243508	2656	UVM_INFO @ 75965065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	40688772057895883066228418588204941513622765981609005115392997326857016243629	444	UVM_INFO @ 60782357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	93841416501329249498639730258857908995704327313973743294552591769029090060531	8385	UVM_INFO @ 27316675463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	110704852979278874546940952563690554855314359300823266706394436761798671427366	7710	UVM_INFO @ 1109919377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	37637340851899769349436840055449834887785840398883801201467890884367590920292	1526	UVM_INFO @ 4236613366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	44164058320717601889343949513889867806639700158293368527496220498538221709803	11698	UVM_INFO @ 195438866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	103274108461061214236972642399417572648198133261538715607993333933191980062550	3076	UVM_INFO @ 317343013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	82294239821133512131731684933436483944891540933097165524412632773139478786039	1526	UVM_INFO @ 493678298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	27944877651391281362032229362010036521501059013301577162902271277905874172260	446	UVM_INFO @ 194769582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	54925564729835177650726626130735201128223045389696438878979906949515632246634	8856	UVM_INFO @ 435194593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	61705253178419962273735316655723965575770586929390608079709314448362723124945	3971	UVM_INFO @ 1082538501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	84014938869685795709945364007160333113836413215490321118582299741356928662381	1050	UVM_INFO @ 361671610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	55970103079130618078701796122223924672844372695934852621570095397264365132104	2500	UVM_INFO @ 97054566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	115314483180732601422574085464026767626213724778476571417908989125450190656972	897	UVM_INFO @ 304524156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	25012020556202778696641838491700874915946564857654504016335456217933234132058	374	UVM_INFO @ 121731443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	11916146520214866954072722146236289833093047452364561160422879426957165019044	4282	UVM_INFO @ 17403294230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	52552827991490049574927541643956367334613261130822034491124905388550585531320	1822	UVM_INFO @ 6718547544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	62349531422575539232691383466568286842412379234206165532526671769377123598250	416	UVM_INFO @ 741961030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	7717601097999219714557464389889446402598541203112541898379773780091015751402	286	UVM_INFO @ 157820253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	30858005607279356299884265455512617786274035100583869570748554272181596436640	6532	UVM_INFO @ 5421331977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	115519597839872058013272544743183547735586620647066939346042236606497707920635	1196	UVM_INFO @ 117923019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	18013528318053678393911764779356358342906925226055796320381508087012860802112	2044	UVM_INFO @ 125876541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	39208033843790709274947021028981451145819054579844872961880891502801384473681	1178	UVM_INFO @ 965514547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	84380834501699866530047123292491957300356015641559081117969977826956310979638	2690	UVM_INFO @ 82054936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	38797261583641599755317657217524699667971405610795963092060604390350226387243	1902	UVM_INFO @ 2365264124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	69882262319835722058964584176990222463318405952549735990703541312320676063977	863	UVM_INFO @ 4896978709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	50305715519382038506308693680720411849238668790908390168722895749877579703892	1578	UVM_INFO @ 231639918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	59998208490905028589260112913706997982912311058137637366391803702130780652583	2350	UVM_INFO @ 215140242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	5939852960417432124639274860976137851970638814753845994091254532172431405579	3074	UVM_INFO @ 1172226508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	17487659115634678340418556948443853434118230557534000128701666940896940719932	1904	UVM_INFO @ 74891988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	88070887783225849987790196701632331630853442787713866071532770407037373174745	806	UVM_INFO @ 144201123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	61096381517325659925758306444205848897629094375322092525057321597928045547065	10102	UVM_INFO @ 2355226904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	113449671742868627339690426529147673329784930718123731100927075124575310646163	24016	UVM_INFO @ 20791437578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	81670037387933734885359693067773175281112407617906340669310429421091371035427	1360	UVM_INFO @ 134423538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	114039937175268640044010234364746614042097006067977179185253234460367318793366	578	UVM_INFO @ 109638741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	94720750511359137248875486228591397508109153733789801603638020687947296270232	3290	UVM_INFO @ 158676466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	26899226680593147201435373999564787882031419691416330751398316511919541473717	940	UVM_INFO @ 55025012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: otp_ctrl_core_reg_block.intr_state				31 test runs
	otp_ctrl_background_chks	88253136189725526233975749496975019428377435730714561976294944857139312164853	2902	UVM_INFO @ 379013140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	66993104430545754314389974286604699587658902423893496602445967498250440202201	5954	UVM_INFO @ 1373597836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_test_access	108642867283139896110298885314631462459202273801951093009807718293974585928971	9699	UVM_INFO @ 1642700843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_key_req	81601361971549506591213675896834675928346723029824608974440925089629500494184	10674	UVM_INFO @ 2688874021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	105725146007454235401570833572100401089936269132710092016077065638472163823213	7185	UVM_INFO @ 830019669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	58033082326594254730428277452709295703527440304998460880558383861688817352437	4144	UVM_INFO @ 5884468632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	74576528876339051613832783681717086614529790991626822064061603467305011222294	3101	UVM_INFO @ 6417132550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	50281912256381162826638235828027597273750178758364383778026990849276996109712	6206	UVM_INFO @ 1848914432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	16877077046210180857424063322670471619354090880250362463525551936747181693187	8664	UVM_INFO @ 14437552572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	13157704914283787343789561520517105778863593573656944726026181329782887285693	5946	UVM_INFO @ 3603505050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	87930118099666582956626125142174261709550230825105435954143023224181075096514	4448	UVM_INFO @ 6015191052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	106829589342638910307925101527835544345086476938125542885262764231972616513963	6217	UVM_INFO @ 640359935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	28362270593172210011975927673153085520724575279489978377561942395230534485401	3636	UVM_INFO @ 2563251350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	82066161660789294854273761036480725467867402459987556420301124395865131607318	6873	UVM_INFO @ 1009475333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	9083001388164717000625103890856372842425841139055396036125783157467231946601	2085	UVM_INFO @ 1008730685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	50848010302134508531144304296147653641667898028527135419298289070597047866455	2934	UVM_INFO @ 100697909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	87602706602096930358914033320536037532872387303413417123133916438486033354348	590	UVM_INFO @ 942021374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	39421851109977766545079025156680422876421619546228241621593687798372777110645	1612	UVM_INFO @ 2075037148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	112485011301917361153308435838245395427415090074984705763340070477242885671813	476	UVM_INFO @ 273542854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	89082158137117361526578105423664481394284796729809083128608298047181911944668	9157	UVM_INFO @ 28729140754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	54095974435532456502394330562817132923696497630517010683583432078407732854799	18808	UVM_INFO @ 14853394704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	9841361876046512490953361466355564027300056719407611744367446222309552297107	943	UVM_INFO @ 510782643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	96402323579679401991392770163987189682928541834232869127904737174199680360951	12456	UVM_INFO @ 34808368209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	20929382981560579348535998508505415494281312123002969284552187327726594202004	172	UVM_INFO @ 93257974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	97929158689867325648539816860970339509733037011576635349866231356604601358124	2086	UVM_INFO @ 77960398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	17252087042260534231877429035398887052236211015016272942696106499715925713397	8175	UVM_INFO @ 14826305547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	47982171578634419247284836309724846632177689322830393742693153199648573136696	13827	UVM_INFO @ 5607143754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	66820481762763878501254634420163008208473819553481403239393212831227786271792	30365	UVM_INFO @ 8141095221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	33320777587213062219426462636605413750655571713873466128532215873135563485483	7644	UVM_INFO @ 1126362975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	74656820703866506188322094868155928183762100965563689463515048495025920768592	15055	UVM_INFO @ 11649429586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	23932636661756811641678282655222550331801277226685134830938898687509772869288	170	UVM_INFO @ 63665380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs []) reg name: otp_ctrl_core_reg_block.direct_access_rdata_				27 test runs
	otp_ctrl_macro_errs	71089374526282289188097660541805240981745245551506206922257266266164270577863	11145	UVM_INFO @ 1656296678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	23460198263986966244183555114098830363238712457377465847133327334001909373267	15458	UVM_INFO @ 1199466033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	105974866880939747173594684867369691549051142643732396443141035597129882919334	7333	UVM_INFO @ 1509302431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	87428378906507099031816453123294698602109441410294244769826328590132923550723	3458	UVM_INFO @ 3680208771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	47509566557029069747086206802765221904266806798255329308125601506814338240732	516	UVM_INFO @ 171150162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	103557102912861520621117337583859299262074912219745959518822968922235313231539	170	UVM_INFO @ 799148766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	41439063944961411328879797292945617063804513325570602289443658855017662715317	1980	UVM_INFO @ 1562931088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	43556736413677853376932949039674248176492378592076287621028292898774509063446	2754	UVM_INFO @ 144695899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	23910168429945325238663608729253979917744459790181247660252229917534057233089	11420	UVM_INFO @ 1013420847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	90576576794699870076122911365437131105785916043150306033808323906173447363992	172	UVM_INFO @ 187254903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	75892823152620292608321260202962276829550376436061953558978997619879943533352	13054	UVM_INFO @ 475509078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	90543285396813751320459854461438976609487461963639171737676378571902347445741	5891	UVM_INFO @ 1144284433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	114468992411501128451749105464205420807027904295665079222837303205378614522615	4066	UVM_INFO @ 444829010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	5100378669176410627678097595613099603765952777432888380569541121288226938029	1536	UVM_INFO @ 398839426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	17912835791802271111403512032761426209618884483984030911168596567965190073422	642	UVM_INFO @ 1376938671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	109365587953080067389368456838975427869750181569245645894610460726411226958758	226	UVM_INFO @ 171284913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	7548180670641404086720113814304109095114615165488091640751371650911304599569	5739	UVM_INFO @ 411138042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	7806668826888179739606195188705803534682844002233447152594451388261235757736	5615	UVM_INFO @ 8274975798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	24776008482565608535796203778244535172745159890420100560183000620368021282739	24950	UVM_INFO @ 27806199424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	834188122332968668676403795261936849037346530490664622069976689402359032616	842	UVM_INFO @ 204134168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	112508322756083079622541181209915760656788528353295441129163073925103945378603	962	UVM_INFO @ 132650559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	74475098368159437891460624614805339104345119875567758687617322418262702982743	3308	UVM_INFO @ 413939826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	103600234921127245440098214766380992156902131462096892022411586073591113768893	1769	UVM_INFO @ 748543676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	85564865926140948949902083379755170359911115942797655681456232931576704331923	2344	UVM_INFO @ 111548215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	30571146081173320674816288508921699524938031172010555397494585102604944024705	7207	UVM_INFO @ 327244974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	76480392977551291897972907155414989289249447176517345473317001629769178433676	63314	UVM_INFO @ 5935092799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	76724954254124947591955082436511280810823960104291076769310406026487075190495	265	UVM_INFO @ 11221480643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:2213) [scoreboard] Check failed item.d_data == exp_data (* [] vs []) d_data mismatch when d_error =				23 test runs
	otp_ctrl_stress_all_with_rand_reset	70402314195411194688961040390047879001903266351617101321861873775615061938099	2052	UVM_INFO @ 13532029752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	99426892567719497043373534532844114158997166169474884206278852207762926003587	91	UVM_INFO @ 119338018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	49189625118907680794782709222903675405260914063788523234851258983655039983016	714	UVM_INFO @ 2942555663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	50534541965049933092974851063021634486036733808489333235330410855674882681687	1297	UVM_INFO @ 1500568588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	107527197549411884733247997527193792821272726170529834964486341640481836950435	2450	UVM_INFO @ 19556111273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	76452068423467036863811699371960328512026233510876473449923689484602152937805	92	UVM_INFO @ 499920497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	5523735961984966833854690743939438035854122183559820629036823781435805116979	209	UVM_INFO @ 312334743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	79781322541422424622664432483845093722044634192186782080039244235450937516532	183	UVM_INFO @ 1043361370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	93083282989688315349371311873880611578272272000150099553749181279588872825377	91	UVM_INFO @ 501631297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	53461140562630383924029771317707927438652859082993563935218899933478548940462	13535	UVM_INFO @ 9947843284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	96823647342898286896683181549074634183151296487237474687186730478209602971996	91	UVM_INFO @ 31077627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	39032536274290540299767688438508654878486707572006726543322637150308678031852	15544	UVM_INFO @ 4537408986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	75572637361453366082216287735183456038456225304517862959344191274310990346104	69209	UVM_INFO @ 23275011313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	114768024016723611130166805342478584787641820616836297022080326463970514200757	3861	UVM_INFO @ 870799438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	21577556937879177089715388603706472976782904340259516911831301110144300146521	5930	UVM_INFO @ 653076366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	76960690717900179791490045044549592516103790506495741639210729748366161983741	53943	UVM_INFO @ 45859284809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	55811126490442547744391048401301747615176732057977316897489124940802961565016	5863	UVM_INFO @ 4076434777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	99314165002605250211673156365284971922534948152680417556244860848817381887373	49124	UVM_INFO @ 3602030292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	106167024287676011457961013393509736524438838269253460140749175772596845010994	3363	UVM_INFO @ 1184919173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	62261526553238329482188291069952662887077154650381590413930439367591830128522	91	UVM_INFO @ 52443147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	9437185029321013786486839746876556239677740093788131220450318139292429823915	19034	UVM_INFO @ 1035367304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	32733518038523472056516658093326727865415450165612226231653877826921357373687	1913	UVM_INFO @ 452561279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	55282311173002035061948335532810283897921322133262184168736676805440512033629	39891	UVM_INFO @ 5471033458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [] vs [*]) Interrupt_pin: OtpErr				14 test runs
	otp_ctrl_dai_lock	66188335632447103839508424763612754635192922965550421036303292776274263616010	5098	UVM_INFO @ 600165228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_key_req	27405486845464416402916199020000896225021813814633231572788007910181734040898	8907	UVM_INFO @ 339056918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	24848024642458663053432876273716270492844563332173788149968350650512885646513	20913	UVM_INFO @ 875831432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_key_req	16774256284778134548432750276376857357963615670035551306886972492285053424242	13638	UVM_INFO @ 1896970124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_background_chks	34148509350901542327715850900160099962829890412405910986130472449734041359223	5291	UVM_INFO @ 1180217461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	20720991554877080825116246524346550573494418011935302488972167781412451135745	11814	UVM_INFO @ 1812999994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	30625118808701192498649522254021055239380589733715702961077679009789431627249	4171	UVM_INFO @ 1069010898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_background_chks	3380606570030452763091166924703144072978673768040005870849540369104479039280	25427	UVM_INFO @ 4976072453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	18148577778638248440354472554633135214268033448187599595194428686355000330450	8148	UVM_INFO @ 230360633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	7995345641878875833074577322977856941518933170111738877120349041277600810425	6227	UVM_INFO @ 3027853165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	21399552941564642474940755556119036098794887088560360703435631316822655017083	19187	UVM_INFO @ 3122337606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	35273251636465243399042260043136619522030611073275176997680604244823198628003	12406	UVM_INFO @ 558531991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	2201272818197146838545505499107646360381291392427731322736247634147518354547	1506	UVM_INFO @ 2279917670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	15362054899288795079938992620312919432974088386955744849113076195505804806696	3546	UVM_INFO @ 173291098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [] vs []) d_data mismatch when d_error =				8 test runs
	otp_ctrl_csr_mem_rw_with_rand_reset	111506707076569316155707450358527333898542772824629651522799097997745878445173	91	UVM_INFO @ 62904622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_csr_mem_rw_with_rand_reset	5494945753079525436965385642761171054028136617906446980841019970192423661303	91	UVM_INFO @ 500887421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	21324582340334312555471691157822019480331766966011530966932535579920035259456	422	UVM_INFO @ 91722670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	107033133828581728346831148030383615843224084510294323378542059904515354085820	1832	UVM_INFO @ 12896087644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	50058388908004774289070986876077851652673440841942373119209475545010310022762	993	UVM_INFO @ 3644965846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	949916758043764845481543179572026332556420608916107779704021478813851682073	164	UVM_INFO @ 10599205632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	3233895906764106679947781821256804225920347488142440190589330109615638552043	91	UVM_INFO @ 61775149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	54418565897175463767547039154216097291629167722277924584900991839444325546817	6127	UVM_INFO @ 4027171559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() \| status_mask) == (item.d_data \| status_mask) (* [] vs []) reg name: status, compare_mask				5 test runs
	otp_ctrl_dai_lock	102967650876012993736370344233466864016532983051886356893842956316011420838754	14817	UVM_INFO @ 22593778781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_req	63971755225828440603352286511426394366504453610881786541900479345709029565921	3591	UVM_INFO @ 146901156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_req	81013110958461107329964333699529485926939307938427005119901987864672188289067	11489	UVM_INFO @ 1520725725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_req	76291376156020113598498928565157271522673937595352706993006499747567419095382	9513	UVM_INFO @ 318625424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	115739056942556529313907307318171295610195469681088859749648527568817925993372	4834	UVM_INFO @ 28047234290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr ed* rdata* readout mismatch				4 test runs
	otp_ctrl_low_freq_read	95426793832374958422800468430073418503546588897983931458132608862715142175968	89	UVM_INFO @ 59304262876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	10485173828656737756561716530860249306869255305206104411531918725731110148195	33475	UVM_INFO @ 24588493082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	59898311197534998198573396290037994028286877037269418465915710894892149633830	90	UVM_INFO @ 58805723193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	70742771686550376012751770340670570691938264773335388137536411465374252603410	9369	UVM_INFO @ 22850031001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed				3 test runs
	otp_ctrl_stress_all	42256272179321152422597247061717410973727402060854563370406126142102868199616	28297	UVM_INFO @ 51426800381 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 51427133715 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 51428133717 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 51429133719 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
	otp_ctrl_stress_all_with_rand_reset	105929940217234958534561412933418778389359653955730024464222927144748515129386	6593	UVM_INFO @ 38174722006 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 38174888673 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 38178555347 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 38179055348 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
	otp_ctrl_stress_all_with_rand_reset	2805443082245897520528026100490812609552336558857577013380165299523798178654	12823	UVM_INFO @ 30146276396 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 30146286813 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 30146943084 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 30146953501 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr c rdata* readout mismatch				2 test runs
	otp_ctrl_stress_all_with_rand_reset	46354270040558824626003944953970044097237620152373089708957550972103505950401	20298	UVM_INFO @ 9976875078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	18246894245230042504963273550018746146219770262209241006696258750997425217921	93	UVM_INFO @ 3672717125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)'				2 test runs
	otp_ctrl_stress_all_with_rand_reset	26480162895114493151151146768133937864560885575971600102570691880801558470295	5107	UVM_ERROR @ 23208643466 ps: (otp_ctrl_if.sv:389) [ASSERT FAILED] CioTestEnOWithDftOff_A UVM_INFO @ 23208643466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	89530019530303216774400657138760060495162650703103586275308187901650372734927	1280	UVM_ERROR @ 3272014514 ps: (otp_ctrl_if.sv:389) [ASSERT FAILED] CioTestEnOWithDftOff_A UVM_INFO @ 3272014514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr ed* rdata* readout mismatch				1 test run
	otp_ctrl_partition_walk	16048162382075914034635184630446495838262130594163852713481521385985540047086	113147	UVM_INFO @ 6596585921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred!				1 test run
	otp_ctrl_sec_cm	43422426704105826050013503724982042407059955143497119118612960190441832786099	605	UVM_INFO @ 14109287541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	otp_ctrl_sec_cm	94409122810857983189372373789906078917865012637276655046214456154403234780482	2475	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr b rdata* readout mismatch				1 test run
	otp_ctrl_stress_all_with_rand_reset	98843630147713245983294252749871086268725582327818585251327656210210647977023	19259	UVM_INFO @ 22137695884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr dc rdata* readout mismatch				1 test run
	otp_ctrl_stress_all_with_rand_reset	107459164123751213001115298805420086768681444200384162004340932362289732672172	7971	UVM_INFO @ 13514802187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr ac rdata* readout mismatch				1 test run
	otp_ctrl_stress_all_with_rand_reset	47763339171858562955588471781517289986045865856204138430949297995464990865999	103	UVM_INFO @ 16395183527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr f rdata* readout mismatch				1 test run
	otp_ctrl_stress_all_with_rand_reset	43650144965010202930807060512689010494644621223684259830270970392253207508246	1684	UVM_INFO @ 7426188906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1365) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_check_error does not trigger!				1 test run
	otp_ctrl_init_fail	75987780635386071270696994176382015521349789122701053650371522429295760812076	960	UVM_INFO @ 2504851161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr rdata* readout mismatch				1 test run
	otp_ctrl_stress_all_with_rand_reset	827965726244814425056792751033605755457380125273546419519278726373594605786	200	UVM_INFO @ 8044657829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---