Simulation Results: rom_ctrl/32kb

 
30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.19 %
  • code
  • 94.61 %
  • assert
  • 97.67 %
  • func
  • 99.29 %
  • block
  • 96.73 %
  • line
  • 97.22 %
  • branch
  • 94.09 %
  • toggle
  • 87.12 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.53%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 5.000s 563.319us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 663.204us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 5.000s 538.238us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 308.818us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 403.792us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 237.039us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 5.000s 538.238us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 403.792us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.000s 168.503us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.000s 581.194us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 5.000s 181.451us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 19.000s 581.834us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 6.000s 1503.993us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 7.000s 582.061us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 11.000s 578.591us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 11.000s 578.591us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.000s 663.204us 1 1 100.00
rom_ctrl_csr_rw 5.000s 538.238us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 403.792us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 539.477us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.000s 663.204us 1 1 100.00
rom_ctrl_csr_rw 5.000s 538.238us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 403.792us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 539.477us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 12168.866us 15 20 75.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 17.000s 3292.669us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 69.000s 786.286us 5 5 100.00
rom_ctrl_tl_intg_err 37.000s 444.385us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 69.000s 786.286us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 69.000s 786.286us 5 5 100.00
sec_cm_checker_ctr_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 12168.866us 15 20 75.00
sec_cm_checker_ctrl_flow_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 12168.866us 15 20 75.00
sec_cm_checker_fsm_local_esc 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 12168.866us 15 20 75.00
sec_cm_compare_ctrl_flow_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 12168.866us 15 20 75.00
sec_cm_compare_ctr_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 12168.866us 15 20 75.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 69.000s 786.286us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 69.000s 786.286us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 5.000s 563.319us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 5.000s 563.319us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 5.000s 563.319us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 37.000s 444.385us 25 25 100.00
sec_cm_bus_local_esc 17 22 77.27
rom_ctrl_corrupt_sig_fatal_chk 64.000s 12168.866us 15 20 75.00
rom_ctrl_kmac_err_chk 6.000s 1503.993us 2 2 100.00
sec_cm_mux_mubi 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 12168.866us 15 20 75.00
sec_cm_mux_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 12168.866us 15 20 75.00
sec_cm_ctrl_redun 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 12168.866us 15 20 75.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 17.000s 3292.669us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 69.000s 786.286us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 16 20 80.00
rom_ctrl_stress_all_with_rand_reset 129.000s 42354.099us 16 20 80.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 5 test runs
rom_ctrl_corrupt_sig_fatal_chk 47626773406273645284560972908319420562826501051969043532257236675296469983197 93
UVM_INFO @ 1050717605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 104181876066887545039336579151970163026645313854932133721549547798250244908521 98
UVM_INFO @ 799854886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 45749994903315506717012903658874862868897244353375711848061943962289216011208 96
UVM_INFO @ 5449499527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 107926964849144668431529079406793391045396666189463947570426748634133293780495 100
UVM_INFO @ 4662673817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 58664618354674563334488964533899258597281398741533922309818905073736436634488 89
UVM_INFO @ 1239226991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 3 test runs
rom_ctrl_stress_all_with_rand_reset 20330339686950688165954525916173656611694618689174578240826271001431418902442 90
UVM_INFO @ 205351115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 39708839045408566972330322890077021973887796142000813192470480961791897331515 90
UVM_INFO @ 179784538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 98897657924787644668143720220643455332767115168685589081315041103605511870485 92
UVM_INFO @ 292997588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:235) [scoreboard] Check failed item.d_data[i**+:*] == exp_data[i**+:*] (* [*] vs * [*]) TLUL ROM read data incorrect 1 test run
rom_ctrl_stress_all_with_rand_reset 78521064992690136092532506975070624588635818612517492938032622001756379577906 96
UVM_INFO @ 92752475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---