Simulation Results: rom_ctrl/64kb

 
30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.19 %
  • code
  • 94.62 %
  • assert
  • 97.67 %
  • func
  • 99.29 %
  • block
  • 96.73 %
  • line
  • 97.22 %
  • branch
  • 94.09 %
  • toggle
  • 87.16 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 7.000s 768.936us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.000s 2020.893us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 7.000s 210.007us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.000s 216.589us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 218.982us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 10.000s 4370.517us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 7.000s 210.007us 5 5 100.00
rom_ctrl_csr_aliasing 5.000s 218.982us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.000s 210.623us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.000s 301.023us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 6.000s 625.753us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 34.000s 1072.200us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 16.000s 543.520us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 11.000s 1928.384us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 12.000s 2081.327us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 12.000s 2081.327us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 9.000s 2020.893us 1 1 100.00
rom_ctrl_csr_rw 7.000s 210.007us 5 5 100.00
rom_ctrl_csr_aliasing 5.000s 218.982us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.000s 374.207us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 9.000s 2020.893us 1 1 100.00
rom_ctrl_csr_rw 7.000s 210.007us 5 5 100.00
rom_ctrl_csr_aliasing 5.000s 218.982us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.000s 374.207us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 161.000s 7477.635us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 37.000s 19116.490us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 240.000s 1169.551us 5 5 100.00
rom_ctrl_tl_intg_err 66.000s 749.637us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 240.000s 1169.551us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 240.000s 1169.551us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 161.000s 7477.635us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 161.000s 7477.635us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 161.000s 7477.635us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 161.000s 7477.635us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 161.000s 7477.635us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 240.000s 1169.551us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 240.000s 1169.551us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 7.000s 768.936us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 7.000s 768.936us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 7.000s 768.936us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 66.000s 749.637us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 161.000s 7477.635us 20 20 100.00
rom_ctrl_kmac_err_chk 16.000s 543.520us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 161.000s 7477.635us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 161.000s 7477.635us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 161.000s 7477.635us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 37.000s 19116.490us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 240.000s 1169.551us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 16 20 80.00
rom_ctrl_stress_all_with_rand_reset 140.000s 6641.015us 16 20 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 4 test runs
rom_ctrl_stress_all_with_rand_reset 7490795374576182290252091923093546540447154425160678527027543811870776947284 91
UVM_INFO @ 4436775277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 82310325824788346660984661993903605834113914474469033418783761937207504677363 90
UVM_INFO @ 333427509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 93855717581551185869921392564242406060258044011551523641812167334807699844686 92
UVM_INFO @ 420753069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 45415691690952404598414798604340039252759680899782974467846726045933412079805 91
UVM_INFO @ 1566761571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---