Simulation Results: rstmgr

 
30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.93 %
  • code
  • 99.59 %
  • assert
  • 98.72 %
  • func
  • 98.49 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.43 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.57%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
rstmgr_smoke 1.920s 69.933us 5 5 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.820s 93.823us 1 1 100.00
csr_rw 5 5 100.00
rstmgr_csr_rw 1.230s 38.192us 5 5 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.840s 66.886us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.910s 51.387us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.260s 95.105us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rstmgr_csr_rw 1.230s 38.192us 5 5 100.00
rstmgr_csr_aliasing 1.910s 51.387us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 5 5 100.00
rstmgr_por_stretcher 2.470s 194.489us 5 5 100.00
sw_rst 5 5 100.00
rstmgr_sw_rst 1.600s 47.388us 5 5 100.00
sw_rst_reset_race 5 5 100.00
rstmgr_sw_rst_reset_race 1.570s 73.791us 5 5 100.00
reset_info 5 5 100.00
rstmgr_reset 7.560s 633.722us 5 5 100.00
cpu_info 5 5 100.00
rstmgr_reset 7.560s 633.722us 5 5 100.00
alert_info 5 5 100.00
rstmgr_reset 7.560s 633.722us 5 5 100.00
reset_info_capture 5 5 100.00
rstmgr_reset 7.560s 633.722us 5 5 100.00
stress_all 5 5 100.00
rstmgr_stress_all 43.860s 5015.086us 5 5 100.00
alert_test 10 10 100.00
rstmgr_alert_test 1.310s 36.054us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rstmgr_tl_errors 3.770s 84.332us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rstmgr_tl_errors 3.770s 84.332us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rstmgr_csr_hw_reset 1.820s 93.823us 1 1 100.00
rstmgr_csr_rw 1.230s 38.192us 5 5 100.00
rstmgr_csr_aliasing 1.910s 51.387us 1 1 100.00
rstmgr_same_csr_outstanding 1.810s 69.256us 5 5 100.00
tl_d_partial_access 12 12 100.00
rstmgr_csr_hw_reset 1.820s 93.823us 1 1 100.00
rstmgr_csr_rw 1.230s 38.192us 5 5 100.00
rstmgr_csr_aliasing 1.910s 51.387us 1 1 100.00
rstmgr_same_csr_outstanding 1.810s 69.256us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rstmgr_sec_cm 46.410s 6814.061us 5 5 100.00
rstmgr_tl_intg_err 7.520s 756.748us 25 25 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 46.410s 6814.061us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 46.410s 6814.061us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
rstmgr_tl_intg_err 7.520s 756.748us 25 25 100.00
sec_cm_scan_intersig_mubi 5 5 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.730s 67.193us 5 5 100.00
sec_cm_leaf_rst_bkgn_chk 24 25 96.00
rstmgr_leaf_rst_cnsty 6.960s 500.921us 24 25 96.00
sec_cm_leaf_rst_shadow 5 5 100.00
rstmgr_leaf_rst_shadow_attack 3.400s 291.157us 5 5 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 46.410s 6814.061us 5 5 100.00
sec_cm_sw_rst_config_regwen 5 5 100.00
rstmgr_csr_rw 1.230s 38.192us 5 5 100.00
sec_cm_dump_ctrl_config_regwen 5 5 100.00
rstmgr_csr_rw 1.230s 38.192us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:* 1 test run
rstmgr_leaf_rst_cnsty 76523683080291389221043746126521646432829746660729454733213116888304069058505 77
UVM_INFO @ 35645736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---