Simulation Results

Simulation Results: rv_dm/use_dmi_interface

30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.13 %

code
84.50 %

assert
96.90 %

func
98.00 %

block
93.74 %

line
94.28 %

branch
83.03 %

toggle
80.31 %

FSM
80.36 %

Validation stages

V1		98.46%
V2		43.33%
V2S		94.00%
V3		5.00%
unmapped		0.00%

128/130 passed

98.46 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	46.000s	746.705us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	42.000s	198.641us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	48.000s	507.592us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	65.000s	40585.853us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	47.000s	331.640us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	53.000s	5175.854us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	65.000s	7858.552us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	222.000s	98552.214us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	136.000s	51945.009us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	38.000s	1125.529us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	41.000s	341.321us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	47.000s	334.446us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	44.000s	225.112us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	45.000s	217.620us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	53.000s	840.343us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	50.000s	309.183us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	47.000s	405.683us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	38.000s	1125.529us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	43.000s	420.317us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	49.000s	306.801us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	47.000s	334.446us	2	2	100.00
rom_read_access				2	2	100.00
	rv_dm_rom_read_access	47.000s	133.766us	2	2	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	36.000s	178.096us	1	1	100.00
csr_rw				5	5	100.00
	rv_dm_csr_rw	43.000s	868.951us	5	5	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	79.000s	7918.558us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	76.000s	3972.886us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rv_dm_csr_mem_rw_with_rand_reset	46.000s	153.808us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rv_dm_csr_aliasing	76.000s	3972.886us	1	1	100.00
	rv_dm_csr_rw	43.000s	868.951us	5	5	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	34.000s	37.570us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	38.000s	48.102us	1	1	100.00

78/180 passed

43.33 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	46.000s	746.705us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	47.000s	384.758us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	49.000s	515.390us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	43.000s	577.900us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	41.000s	2276.778us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	62.000s	4135.157us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	51.000s	71.768us	0	20	0.00
bad_sba				0	20	0.00
	rv_dm_bad_sba_tl_access	65.000s	13217.900us	0	20	0.00
sba_autoincrement				5	20	25.00
	rv_dm_autoincr_sba_tl_access	192.000s	76656.770us	5	20	25.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	38.000s	91.709us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	44.000s	2655.684us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	42.000s	140.013us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	41.000s	328.410us	0	5	0.00
tap_ctrl_transitions				11	11	100.00
	rv_dm_tap_fsm	42.000s	9521.791us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	112.000s	18477.645us	10	10	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	36.000s	139.585us	1	1	100.00
stress_all				0	20	0.00
	rv_dm_stress_all	10801.000s	0.000us	0	20	0.00
alert_test				10	10	100.00
	rv_dm_alert_test	48.000s	67.054us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rv_dm_tl_errors	53.000s	184.891us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rv_dm_tl_errors	53.000s	184.891us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rv_dm_csr_aliasing	76.000s	3972.886us	1	1	100.00
	rv_dm_csr_hw_reset	36.000s	178.096us	1	1	100.00
	rv_dm_csr_rw	43.000s	868.951us	5	5	100.00
	rv_dm_same_csr_outstanding	48.000s	4693.632us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rv_dm_csr_aliasing	76.000s	3972.886us	1	1	100.00
	rv_dm_csr_hw_reset	36.000s	178.096us	1	1	100.00
	rv_dm_csr_rw	43.000s	868.951us	5	5	100.00
	rv_dm_same_csr_outstanding	48.000s	4693.632us	5	5	100.00

V2S

47/50 passed

94.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	rv_dm_sec_cm	42.000s	1938.059us	5	5	100.00
	rv_dm_tl_intg_err	63.000s	7071.567us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	rv_dm_tl_intg_err	63.000s	7071.567us	25	25	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	44.000s	2655.684us	2	2	100.00
	rv_dm_debug_disabled	34.000s	61.832us	2	2	100.00
sec_cm_lc_dft_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	44.000s	2655.684us	2	2	100.00
	rv_dm_debug_disabled	34.000s	61.832us	2	2	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	46.000s	746.705us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				7	10	70.00
	rv_dm_buffered_enable	48.000s	134.900us	7	10	70.00
sec_cm_sba_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	44.000s	180.277us	4	4	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	44.000s	180.277us	4	4	100.00
sec_cm_exec_ctrl_mubi				7	10	70.00
	rv_dm_buffered_enable	48.000s	134.900us	7	10	70.00

1/20 passed

5.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	20	5.00
	rv_dm_stress_all_with_rand_reset	77.000s	5515.927us	1	20	5.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	355.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				40 test runs
	rv_dm_sba_tl_access	66081659401692273020425110162543959744828021914285508030072272130611214659319	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24254
	rv_dm_autoincr_sba_tl_access	3001107808655043412748669809547587739609588474017804688286547140923752190950	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24252
	rv_dm_sba_tl_access	106176975314955038070926048695010189755360523395369616313898704880632627641325	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24199
	rv_dm_bad_sba_tl_access	1905283504421350049955087544908425118945764542111036684057766477586365483659	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24294
	rv_dm_sba_tl_access	15565939548922797572131495954952737035480204421328455145670731987579906456911	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24249
	rv_dm_bad_sba_tl_access	26919004195468172945366763668972068564309420979849834616207554354830980929565	120	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24329
	rv_dm_autoincr_sba_tl_access	32227565519801932040861443522258658303988430851986496598175445894455565348081	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10080
	rv_dm_sba_tl_access	19362111997665677465452643168134491550156927880976107658101341023012980200843	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24223
	rv_dm_bad_sba_tl_access	10987769780186000956337630605288335970783113499872737095666386106965817593530	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24279
	rv_dm_sba_tl_access	46393707593101632068971503693348516585286537496686555218561900582335152236637	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24262
	rv_dm_bad_sba_tl_access	115369786101718855370717303264933000394661434851943444012273116272890250530386	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24227
	rv_dm_sba_tl_access	57729093811513340689151357646993461941173590938141640032845650186970179085148	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24191
	rv_dm_bad_sba_tl_access	54388519494619013948077953182162209918997963525574276435626039798776557225279	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24242
	rv_dm_sba_tl_access	50626055299570885493328270688344884375421077325085265003968622240206169695766	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24165
	rv_dm_sba_tl_access	50633681408404935772511589414527857054230143408156641993828208409149868147195	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24243
	rv_dm_autoincr_sba_tl_access	63339349468296386495309802070058030391416215221322764680444569819338677521266	123	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24354
	rv_dm_sba_tl_access	88023871967113586595982460415366157510225193136268236427955436924577398529558	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24194
	rv_dm_bad_sba_tl_access	42922688259049476840773583552802419580661930146874024895124235563290736603931	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24338
	rv_dm_sba_tl_access	73135986058102662002593185625670561170462950156001932340627847141340936675935	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10091
	rv_dm_sba_tl_access	25186924213601780672358328667437019163203012998234325617528211897773517726579	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24237
	rv_dm_sba_tl_access	39696909846865626022330086949429436795967023220439495170127189903753430067793	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24199
	rv_dm_bad_sba_tl_access	58113998049702012484953723007160875943829917709274554500140757531652312287340	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24376
	rv_dm_autoincr_sba_tl_access	17425151044136867044715069224739870917999447403733983074915223957439268146215	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24156
	rv_dm_sba_tl_access	67084307709380262652971492983135314492368162372103808633462263452391412715979	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24187
	rv_dm_bad_sba_tl_access	36163931162801167401633538428621832096973969462137136875676350772313452157738	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24298
	rv_dm_autoincr_sba_tl_access	20883253115698890560205980175583586781578507009878556966569272825850285336797	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24168
	rv_dm_sba_tl_access	77219170611518705022718593175544648442283168663230154588017543561561307673428	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24223
	rv_dm_bad_sba_tl_access	87542989738403381429210738477479267284920834602165936262135602203782364446276	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24272
	rv_dm_sba_tl_access	102267635676031581075558306480026908010247956949708721014284671226194228587809	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24170
	rv_dm_bad_sba_tl_access	15106782258808298435842164014204944972702687302102406378178977970507484133126	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24183
	rv_dm_sba_tl_access	53004054894054743561240612106890854402783198947025479224731300432537300401577	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24250
	rv_dm_autoincr_sba_tl_access	40718855199984422322305137322521979011353898975101705511522860403989660509017	126	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24119
	rv_dm_sba_tl_access	52845482334415600200176191747338204714760143475242913968419195532636478651073	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24212
	rv_dm_bad_sba_tl_access	35209148974586517464221351794793053117244138116418433976981253278545036629420	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24187
	rv_dm_autoincr_sba_tl_access	25661713653430622141338294425299351771669682810238856342736239049865614645675	93	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24144
	rv_dm_sba_tl_access	46425036140768671393277606744887942111297626853902723713495571533233345358971	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24242
	rv_dm_autoincr_sba_tl_access	102689842503042096516361253072007803750792015260067883693061832533788539604960	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24270
	rv_dm_sba_tl_access	14208114710039310510069371598762546816385524754786925782589441006977140498728	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24167
	rv_dm_sba_tl_access	57791445002162441320294559669821725642694747996687579156981261351867492277903	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24210
	rv_dm_bad_sba_tl_access	108126585422349126506468153869226826903873684047453455013490787921702973215813	120	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24305
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				35 test runs
	rv_dm_delayed_resp_sba_tl_access	109974882960828073170496463138328556889685917559321439220198707148574415868139	107	UVM_INFO @ 173027274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	75932768822060797061043708465464365040054989572741767977685011424102653821960	107	UVM_INFO @ 119225733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	111976205866010808127296651104839205900066903503733873401119178183217536467855	107	UVM_INFO @ 71768220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	102237895680410771944223841527295214573796880525067630837883299628985918586514	107	UVM_INFO @ 102838475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	19423365106459602092947025116380450050865233954971044141390674280640221216380	107	UVM_INFO @ 150190560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	62936446007289495829317054385718200229094283255534207070229513990819103354990	107	UVM_INFO @ 343490821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	37067459561474490613300332885653272766288938400878295071084426395183868890447	107	UVM_INFO @ 124009996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	47999036349949885357699398037910049206931139903591448105279558628498149229218	107	UVM_INFO @ 101259246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	53249178194792984691413107153986365360160058696172076693586737450734403138003	107	UVM_INFO @ 88159289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	93834093209214052053089097174987842599933458431266428214797526610075369308771	107	UVM_INFO @ 281184572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	89442144541715080979598736418090691159962863134819083303722845924909610645343	107	UVM_INFO @ 122555976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	57361211199665391494079077097968223080594988042366730958098167798927657143208	119	UVM_INFO @ 1646110358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	84903190781224866423712841599982101775054151161204492757470274743754115359934	107	UVM_INFO @ 316766088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	106803796335745269407325631709438034043003106360330175253089695331513201061681	107	UVM_INFO @ 750148159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	876746821405570899799719774249586698145710918508305796539080173667446614550	107	UVM_INFO @ 74094533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	64597665490493222929797222509454560009130378960945751647205382446982974969438	107	UVM_INFO @ 119270666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	13854608208199767293982388309874448980510941424536997775348165423439971090369	107	UVM_INFO @ 48629577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	113489434653394109778757273602097536406291938792121252355211193659642394165670	107	UVM_INFO @ 124394994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	102970263496990256784066552100040491313985918012460360761229448314182534490305	107	UVM_INFO @ 345876586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	10123786371364855185297940862883982514000408693006841792926516836621817711380	107	UVM_INFO @ 365171869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	10224394534873135881871253203245482434860975428130522207928647226965471890546	107	UVM_INFO @ 85228716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	23783781500998576851201709415970544312174961436109516501429604228216620868917	107	UVM_INFO @ 237690514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	14907668784542716097633776498109630589046657637468410413394731204417092549207	107	UVM_INFO @ 533157248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	6403544771618601613663834993284250859856052748663297915188384842522679150749	107	UVM_INFO @ 95787951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	78360150449994543228674178709158921641700215443190832651756514373831202667914	107	UVM_INFO @ 361949495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	18253925451316691815694818381105405762295113542429152222620095436028945469696	107	UVM_INFO @ 82193217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	50220425096429620780674374799340181339445559397084095567785510494269007424168	107	UVM_INFO @ 134064931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	7701976879824182897670761951111800826174970068802205288567610758163104241830	107	UVM_INFO @ 61100675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	61020260558788176418881833254279626079945463691797006269036080673089304339172	107	UVM_INFO @ 68350791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	34854763883944582494425247604149290515330987162840182886478935440882860487287	107	UVM_INFO @ 163013507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	10195686792458790167253352208600260616300511237738213451535559850033372333637	107	UVM_INFO @ 146896123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	70851812424302157933740702062621443598374714167217541682882213259104545526239	107	UVM_INFO @ 52907776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	1780557834264728602189116217898338653527344230980404629819093124466307282906	107	UVM_INFO @ 66205969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	51964713525123608669090884922295062070147480453870418939012111026101338927181	107	UVM_INFO @ 105897224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	49384615393694577583244162142111647341777813705968319464608551034610190399153	107	UVM_INFO @ 79999681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				16 test runs
	rv_dm_hart_unavail	33801392125305029317144615550609284028206304077543788643899021392663295163212	87	UVM_INFO @ 74022754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	82392280326425807601155549033152761665294993070928048658457708205584721252018	136	UVM_INFO @ 5515927033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	70710082432824605449986989531858721870344920887086891520795701524583391491647	87	UVM_INFO @ 65971695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	31008136899651695916089079758426994946978033573101576930859920425734989354625	107	UVM_INFO @ 2509501494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	51536014008997419635563730339143637476655416068303953047117676943921411692796	87	UVM_INFO @ 79815264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	68132041713837572159681707897628892152467531662442543579425353639338945894427	88	UVM_INFO @ 57848377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	12782159712237924050975028593136962940319843361118194193896967888909771701515	87	UVM_INFO @ 63537472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	83530438536061278448214101292237729748834476264018096204176220527947897649190	87	UVM_INFO @ 328410226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	97943287925252411560348098535241215509600155384002261613660587127541228159679	99	UVM_INFO @ 799367899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	25159926530054082166800490950677251244959662114238204920898875804900203015345	88	UVM_INFO @ 432635403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	44264198851766132734884047847123000807818971258668604622555039586967305512033	92	UVM_INFO @ 375166352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	50419151005230882446670666910495550017983621824003051047814357396999134290311	92	UVM_INFO @ 1859122077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	66117402956580650377937564804992438143248521804102033636369567429786773445496	97	UVM_INFO @ 286914778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	10336644228363208609837012801738770868067640092084348621982818846636694600147	91	UVM_INFO @ 262828411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	8446014697944579601200675220200784523664757922794232649955392221576709131284	118	UVM_INFO @ 1182496485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	3111236915183880848157762826653466446747223364102765429957819385293679363651	91	UVM_INFO @ 2078454382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				15 test runs
	rv_dm_jtag_dmi_debug_disabled	50323699426018693023898083118699898140464799467270857200543238445987293611885	87	UVM_INFO @ 608741653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	17021258735259943352870487676644895612446585677629977362577619780173284770949	87	UVM_INFO @ 91709398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	12519400424670212641840584596205792867428105655245183068720377172513716456278	94	UVM_INFO @ 2118448070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	88200444607118492129922455563886212516349099376347277928863751977857095918024	94	UVM_INFO @ 460616240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	48450322744882215666201230799481760862829517481438897525488164335641803514854	93	UVM_INFO @ 324596987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	4695895813799248687515744957755864244430548914163348810377614157640112434066	88	UVM_INFO @ 194016315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	92769331450227815780552785966501727975116559596429081263618621860130398522193	104	UVM_INFO @ 1239231235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	93871077211886772786217972488913951032578415731263083924591451078087892092497	92	UVM_INFO @ 3346205842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	92512239546945065838052557062020085679114001564895264407660872182784819348907	89	UVM_INFO @ 369144001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	114839297809397600094948195634640134811139457824534901713293656269553742581660	94	UVM_INFO @ 707757188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	45177259343916531422249484780333457815133685979146839842091689503637417584960	91	UVM_INFO @ 1936987436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	49481719097508199585416507772677435974328813603345071009132322935838903463324	88	UVM_INFO @ 411126968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	39961027346185533334534829306181838861038717395220430242119407384591604340492	114	UVM_INFO @ 1071638502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	115275045624156729209447051391974752484145298162943973565516526165599462619300	89	UVM_INFO @ 1020736020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	52596969785075747085498458120798931809733152385047195005294492184742729125700	93	UVM_INFO @ 2079367744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				11 test runs
	rv_dm_mem_tl_access_resuming	47410221065645139536681045197988293864741070630691045312097446867808726597741	87	UVM_INFO @ 225112309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	17029258864060410818470937896829017240028963517748461475530586314814820583223	94	UVM_INFO @ 4225682680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	84050986047881397879575802604628134591366591411146458899623115461435820747649	87	UVM_INFO @ 134109891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	111970230021488484489341467370380502319591591687537420808805014099856756965869	88	UVM_INFO @ 126873429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	20896355103499670013316134762562127130899496363364017421184963196424357627018	88	UVM_INFO @ 205490557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	43779692830265771829559844598898860636272803932519893137608359408626226663937	102	UVM_INFO @ 959719287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	41497027002934076849268411171666395783738902305654732952355306300241292050443	93	UVM_INFO @ 3031718854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	63679444268988068975286829303567179785084502044764436465860497257289190404055	89	UVM_INFO @ 687510095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	5650038684411450275972973568664078765928338676724544348791497437382191147811	104	UVM_INFO @ 1091178454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	34357475014293648336888598350134566556041974585249816310730942983570339322042	95	UVM_INFO @ 669363332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	1384292654422190567658738650910597018357167973412486329920582012661683251939	99	UVM_INFO @ 229472439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])				3 test runs
	rv_dm_buffered_enable	106383773566783995310867780507232868350756941341266638522981551395608879798360	91	UVM_INFO @ 148276291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	79658411669848457058805573753869521318139048795107367547883845156233584051072	93	UVM_INFO @ 110069301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	49002882142962562052672999625130174092943552207179117183056231044682072943155	92	UVM_INFO @ 436220760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done)				3 test runs
	rv_dm_stress_all_with_rand_reset	34951947107034742795870210835007490521429092090640260970388191792925515969542	113	UVM_INFO @ 3670155927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	99660503050650128496081102686297542827528647446883861189224154402502413353529	122	UVM_INFO @ 3592794727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	6535563667584753296656928924826618403584398039893081016411978947298183870196	102	UVM_INFO @ 3668023059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	rv_dm_scanmode	14025753563866304396394857639329062543578351237768923486708380699844963926212	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	29499565742192333100535780670932222433848840246218767071521800034629408849727	109	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				2 test runs
	rv_dm_stress_all	95370045428481920632871989680447011343701361945828148268521291341645967987609	None
	rv_dm_stress_all	52431854467213130506596150519421907415576186745699627668066808082297944008490	None