Simulation Results: rv_timer

 
30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 98.09 %
  • code
  • 95.85 %
  • assert
  • 98.42 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
84.25%
V2S
100.00%
V3
42.50%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 2.000s 121.234us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 36.603us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 1.000s 55.680us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 2952.242us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 39.705us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 43.961us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 1.000s 55.680us 5 5 100.00
rv_timer_csr_aliasing 2.000s 39.705us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 20 0.00
rv_timer_random_reset 13.000s 38258.214us 0 20 0.00
disabled 20 20 100.00
rv_timer_disabled 4.000s 1167.351us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 411.000s 293900.053us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 411.000s 293900.053us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 11.000s 6978.146us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 2.000s 16.773us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 2.000s 104.189us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 3.000s 114.011us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 3.000s 114.011us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 36.603us 1 1 100.00
rv_timer_csr_rw 1.000s 55.680us 5 5 100.00
rv_timer_csr_aliasing 2.000s 39.705us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 27.894us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 36.603us 1 1 100.00
rv_timer_csr_rw 1.000s 55.680us 5 5 100.00
rv_timer_csr_aliasing 2.000s 39.705us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 27.894us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 2.000s 252.599us 5 5 100.00
rv_timer_tl_intg_err 2.000s 158.875us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 2.000s 158.875us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 2 10 20.00
rv_timer_min 2.000s 1292.120us 2 10 20.00
max_value 1 10 10.00
rv_timer_max 3.000s 844.441us 1 10 10.00
stress_all_with_rand_reset 14 20 70.00
rv_timer_stress_all_with_rand_reset 66.000s 18192.278us 14 20 70.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 28 test runs
rv_timer_min 93350488455687256580032270313219847044570824486201874550519378328695999374616 84
UVM_INFO @ 114549418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 63238690154334313630336860254081691405132998223854991964082198146898156199953 85
UVM_INFO @ 491417494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 14815927600137942704135599598407852019054855825161081664264223905050755593196 85
UVM_INFO @ 1292120204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 76123521930460333676591608000223406749766416663603006338861129044686618630593 84
UVM_INFO @ 171834326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 112415957411863046484256298377404075640532519146539950595774225524537765188004 84
UVM_INFO @ 71156183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 85941072916282237036305907023145531693817983023623044403574436926730623253676 87
UVM_INFO @ 9711415040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 62913950104341662194471012219761157672183902150120576559507707027922401499928 85
UVM_INFO @ 73178988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 75765678510724196578474472894218550580442469392846483959515923560530079220828 84
UVM_INFO @ 2051053804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 97487133520725454707558602436556101546230764553494552817630540568579915591897 84
UVM_INFO @ 137023210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 58937689115289250539297770770629288422769254940577965193993537703994477243334 85
UVM_INFO @ 78642111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 77586703172760206262593352442816573636148272811727095064717706159048384472828 84
UVM_INFO @ 925580580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 17497495144812364376751089687603111805772035653996940822481045150670093012029 85
UVM_INFO @ 232717493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 25151176782447473230778178539187381473577873432798928632338565496611453365322 84
UVM_INFO @ 273569499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 18042528014263905510490402675079263262902265955000218044144048033442778843065 88
UVM_INFO @ 77728613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 90029863731517569941222733540791969822920577902899683654207277841688701716765 84
UVM_INFO @ 97188049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 17919882989989214823929023674072224899109484264144659008788526960848464191903 87
UVM_INFO @ 557308147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 4739002512157644894643031348347686638745946362741385226692948342094234065751 84
UVM_INFO @ 1483534338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 34763023618812209634064616556078620408640546668859023740167474310976412619576 84
UVM_INFO @ 678681919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 18880815891625943146823794070034917749206297125186338676338989058948600943901 85
UVM_INFO @ 367478980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 20250130082834008540296197453731276035122866603651749227954756938809054889564 84
UVM_INFO @ 38258214322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 94305274003074808415976090748831721821365337688652031075906500410739935870516 85
UVM_INFO @ 105911968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 47876779369637035878395747765198236550363855667293066189054614253395021317757 85
UVM_INFO @ 194325229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 1936179433621597827917747348827142867427061313203806032284452235364644864800 85
UVM_INFO @ 632009535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 114730290399631067284505442430111008817553918835719547066811609140234271027397 84
UVM_INFO @ 2721540256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 32212955129017898314962100085192169881830167816695778602453470674191131550256 84
UVM_INFO @ 93893323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 89214427070050323541547735213426992099722719617108427229891633437218723017535 84
UVM_INFO @ 321762758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 10229533486014906785459188004165024277516504399580242606325522226010796387195 84
UVM_INFO @ 638509541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 78116958119966873277494839224279264957833259137642748103695405813121949927434 85
UVM_INFO @ 463538851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 8 test runs
rv_timer_max 98471134512026122847822403873362014933676519752856096062183422243804174350116 84
UVM_INFO @ 177347200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 7187279775061123770379667326215489354776202437740028538352046812452700698324 84
UVM_INFO @ 43310788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 28599658236089518768917321224931684467178592362642824408499617113855065631514 84
UVM_INFO @ 201224307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 97219827529637384294661060786856389049840053305127874738158139281642391271699 84
UVM_INFO @ 844441103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 89164030566062057214219333123738367487881256230039757981457780180714122345164 85
UVM_INFO @ 176170162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 91965308092740083568668384462539992406758370593683128059175013624884606358612 84
UVM_INFO @ 87521834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 98199431431862216106859078344287605288542485109258221466951301285428992447745 84
UVM_INFO @ 98193979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 43689295681627654021341965319027390735340886865282187568166550123839491004487 84
UVM_INFO @ 555442727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 3 test runs
rv_timer_stress_all_with_rand_reset 81352836360655009029419883132329612725093762746084340165007830329515475631655 249
UVM_INFO @ 41606491773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 84859344428902137062418675281136015998590369105900442861446925694616377044673 236
UVM_INFO @ 4374697587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 89089604886668679698611338953220571060009610415132927747602890731677809819693 450
UVM_INFO @ 9559393339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
rv_timer_stress_all_with_rand_reset 83277210523437455135855021588414733246966438683930197850322875484248340975471 231
UVM_INFO @ 10255738142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 82970894382963038399252757888526077523450942337737690476422158624129213032926 214
UVM_INFO @ 5147354889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 93715122726128164833780809373622548671045008152187623040791906481513723651835 175
UVM_INFO @ 3182949866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:347) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 62143967901629125567429224143648235588655905024515619435142260153209293149767 85
UVM_INFO @ 45057374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---