Simulation Results: spi_host

 
30/05/2026 03:06:07 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.13 %
  • code
  • 95.03 %
  • assert
  • 96.59 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 135.000s 3416.034us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 49.126us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 20.980us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 4.000s 452.591us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 23.369us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 70.975us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 20.980us 5 5 100.00
spi_host_csr_aliasing 1.000s 23.369us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 24.391us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 76.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 23.317us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 7.000s 419.370us 10 10 100.00
spi_host_error_cmd 2.000s 29.629us 10 10 100.00
spi_host_event 267.000s 9272.634us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 9.000s 213.149us 10 10 100.00
speed 10 10 100.00
spi_host_speed 9.000s 213.149us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 9.000s 213.149us 10 10 100.00
upper_range_clkdiv 5 5 100.00
spi_host_upper_range_clkdiv 361.000s 8843.918us 5 5 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 9.000s 1038.718us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 37.420us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 9.000s 213.149us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 9.000s 213.149us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 135.000s 3416.034us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 135.000s 3416.034us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 89.000s 2090.866us 10 10 100.00
spien 10 10 100.00
spi_host_spien 23.000s 2263.420us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 809.000s 296601.384us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 25.000s 2028.129us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 7.000s 419.370us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 39.085us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 32.792us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 238.743us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 238.743us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 49.126us 1 1 100.00
spi_host_csr_rw 2.000s 20.980us 5 5 100.00
spi_host_csr_aliasing 1.000s 23.369us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 92.836us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 49.126us 1 1 100.00
spi_host_csr_rw 2.000s 20.980us 5 5 100.00
spi_host_csr_aliasing 1.000s 23.369us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 92.836us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 1058.831us 25 25 100.00
spi_host_sec_cm 2.000s 83.169us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 1058.831us 25 25 100.00