Simulation Results: ac_range_check

 
06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.32 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.67 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
96.23%
V2
97.73%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 19 20 95.00
ac_range_check_smoke 56.000s 6908.181us 19 20 95.00
ac_range_check_smoke_racl 19 20 95.00
ac_range_check_smoke_racl 66.000s 4546.864us 19 20 95.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 72.142us 1 1 100.00
csr_rw 5 5 100.00
ac_range_check_csr_rw 3.000s 48.420us 5 5 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 58.000s 5666.633us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 34.000s 4772.509us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 129.986us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
ac_range_check_csr_rw 3.000s 48.420us 5 5 100.00
ac_range_check_csr_aliasing 34.000s 4772.509us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 57.189us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 66.000s 6065.396us 1 1 100.00
stress_all 8 10 80.00
ac_range_check_stress_all 272.000s 22298.135us 8 10 80.00
alert_test 10 10 100.00
ac_range_check_alert_test 29.000s 29.640us 10 10 100.00
intr_test 10 10 100.00
ac_range_check_intr_test 2.000s 61.848us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
ac_range_check_tl_errors 6.000s 945.898us 25 25 100.00
tl_d_illegal_access 25 25 100.00
ac_range_check_tl_errors 6.000s 945.898us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 72.142us 1 1 100.00
ac_range_check_csr_rw 3.000s 48.420us 5 5 100.00
ac_range_check_csr_aliasing 34.000s 4772.509us 1 1 100.00
ac_range_check_same_csr_outstanding 6.000s 719.402us 5 5 100.00
tl_d_partial_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 72.142us 1 1 100.00
ac_range_check_csr_rw 3.000s 48.420us 5 5 100.00
ac_range_check_csr_aliasing 34.000s 4772.509us 1 1 100.00
ac_range_check_same_csr_outstanding 6.000s 719.402us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 2159.138us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 2159.138us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 2159.138us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 2159.138us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 144.000s 9675.037us 20 20 100.00
tl_intg_err 30 30 100.00
ac_range_check_sec_cm 2.000s 12.561us 5 5 100.00
ac_range_check_tl_intg_err 15.000s 1641.099us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
ac_range_check_stress_all_with_rand_reset 350.000s 2117.478us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 54.000s 1532.017us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 3 test runs
ac_range_check_smoke_racl 92955559761686537810329110643818380367073923771921697083143730272422799042994 4202
UVM_INFO @ 2328724177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 4960196956440699428154073491700013470356816585440595861554316333690078166576 23357
UVM_INFO @ 2550154031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke 9718728073351131008012266281356068053237696797770138333933933500865583905119 4762
UVM_INFO @ 28827385749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (ac_range_check_predictor.sv:163) [predict] Unable to get any item from tl_filt_d_chan_fifo. 1 test run
ac_range_check_stress_all 49747001563523561184015341125053696924025782707366078103789746763477686222372 23579
UVM_INFO @ 100271803798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---