Simulation Results: aes/gcm_masked

 
06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.50 %
  • code
  • 98.09 %
  • assert
  • 98.43 %
  • func
  • 95.99 %
  • block
  • 98.15 %
  • line
  • 99.26 %
  • branch
  • 94.96 %
  • toggle
  • 98.13 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.37%
V2S
93.42%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 63.593us 1 1 100.00
smoke 10 10 100.00
aes_smoke 6.000s 99.669us 10 10 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 142.660us 1 1 100.00
csr_rw 5 5 100.00
aes_csr_rw 3.000s 100.560us 5 5 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 191.997us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 216.058us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
aes_csr_mem_rw_with_rand_reset 3.000s 63.987us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
aes_csr_rw 3.000s 100.560us 5 5 100.00
aes_csr_aliasing 3.000s 216.058us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 69 70 98.57
aes_smoke 6.000s 99.669us 10 10 100.00
aes_config_error 7.000s 949.617us 49 50 98.00
aes_stress 9.000s 227.680us 10 10 100.00
key_length 69 70 98.57
aes_smoke 6.000s 99.669us 10 10 100.00
aes_config_error 7.000s 949.617us 49 50 98.00
aes_stress 9.000s 227.680us 10 10 100.00
back2back 35 35 100.00
aes_stress 9.000s 227.680us 10 10 100.00
aes_b2b 21.000s 987.617us 25 25 100.00
backpressure 10 10 100.00
aes_stress 9.000s 227.680us 10 10 100.00
multi_message 94 95 98.95
aes_smoke 6.000s 99.669us 10 10 100.00
aes_config_error 7.000s 949.617us 49 50 98.00
aes_stress 9.000s 227.680us 10 10 100.00
aes_alert_reset 15.000s 185.900us 25 25 100.00
failure_test 84 85 98.82
aes_man_cfg_err 4.000s 65.653us 10 10 100.00
aes_config_error 7.000s 949.617us 49 50 98.00
aes_alert_reset 15.000s 185.900us 25 25 100.00
trigger_clear_test 10 10 100.00
aes_clear 8.000s 347.553us 10 10 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 10.000s 289.855us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 10.000s 389.374us 1 1 100.00
reset_recovery 25 25 100.00
aes_alert_reset 15.000s 185.900us 25 25 100.00
stress 10 10 100.00
aes_stress 9.000s 227.680us 10 10 100.00
sideload 20 20 100.00
aes_stress 9.000s 227.680us 10 10 100.00
aes_sideload 12.000s 241.684us 10 10 100.00
deinitialization 10 10 100.00
aes_deinit 24.000s 1380.960us 10 10 100.00
stress_all 9 10 90.00
aes_stress_all 51.000s 8507.968us 9 10 90.00
gcm_save_and_restore 100 100 100.00
aes_gcm_save_restore 15.000s 881.293us 100 100 100.00
alert_test 10 10 100.00
aes_alert_test 3.000s 57.571us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
aes_tl_errors 4.000s 86.889us 25 25 100.00
tl_d_illegal_access 25 25 100.00
aes_tl_errors 4.000s 86.889us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
aes_csr_hw_reset 2.000s 142.660us 1 1 100.00
aes_csr_rw 3.000s 100.560us 5 5 100.00
aes_csr_aliasing 3.000s 216.058us 1 1 100.00
aes_same_csr_outstanding 3.000s 275.452us 5 5 100.00
tl_d_partial_access 12 12 100.00
aes_csr_hw_reset 2.000s 142.660us 1 1 100.00
aes_csr_rw 3.000s 100.560us 5 5 100.00
aes_csr_aliasing 3.000s 216.058us 1 1 100.00
aes_same_csr_outstanding 3.000s 275.452us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 10 10 100.00
aes_reseed 11.000s 371.645us 10 10 100.00
fault_inject 595 660 90.15
aes_fi 6.000s 1163.813us 10 10 100.00
aes_control_fi 62.043s 0.000us 268 300 89.33
aes_cipher_fi 61.000s 0.000us 317 350 90.57
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 3.000s 411.647us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 3.000s 411.647us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 3.000s 411.647us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 3.000s 411.647us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 5.000s 1261.039us 20 20 100.00
tl_intg_err 30 30 100.00
aes_sec_cm 9.000s 1909.778us 5 5 100.00
aes_tl_intg_err 4.000s 241.266us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
aes_tl_intg_err 4.000s 241.266us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 25 25 100.00
aes_alert_reset 15.000s 185.900us 25 25 100.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 411.647us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 411.647us 20 20 100.00
sec_cm_main_config_sparse 134 145 92.41
aes_smoke 6.000s 99.669us 10 10 100.00
aes_stress 9.000s 227.680us 10 10 100.00
aes_alert_reset 15.000s 185.900us 25 25 100.00
aes_core_fi 88.000s 10044.853us 89 100 89.00
sec_cm_gcm_config_sparse 248 260 95.38
aes_gcm_save_restore 15.000s 881.293us 100 100 100.00
aes_config_error 7.000s 949.617us 49 50 98.00
aes_stress 9.000s 227.680us 10 10 100.00
aes_core_fi 88.000s 10044.853us 89 100 89.00
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 411.647us 20 20 100.00
sec_cm_aux_config_regwen 20 20 100.00
aes_readability 3.000s 102.135us 10 10 100.00
aes_stress 9.000s 227.680us 10 10 100.00
sec_cm_key_sideload 20 20 100.00
aes_stress 9.000s 227.680us 10 10 100.00
aes_sideload 12.000s 241.684us 10 10 100.00
sec_cm_key_sw_unreadable 10 10 100.00
aes_readability 3.000s 102.135us 10 10 100.00
sec_cm_data_reg_sw_unreadable 10 10 100.00
aes_readability 3.000s 102.135us 10 10 100.00
sec_cm_key_sec_wipe 10 10 100.00
aes_readability 3.000s 102.135us 10 10 100.00
sec_cm_iv_config_sec_wipe 10 10 100.00
aes_readability 3.000s 102.135us 10 10 100.00
sec_cm_data_reg_sec_wipe 10 10 100.00
aes_readability 3.000s 102.135us 10 10 100.00
sec_cm_data_reg_key_sca 10 10 100.00
aes_stress 9.000s 227.680us 10 10 100.00
sec_cm_key_masking 10 10 100.00
aes_stress 9.000s 227.680us 10 10 100.00
sec_cm_main_fsm_sparse 10 10 100.00
aes_fi 6.000s 1163.813us 10 10 100.00
sec_cm_main_fsm_redun 620 685 90.51
aes_fi 6.000s 1163.813us 10 10 100.00
aes_control_fi 62.043s 0.000us 268 300 89.33
aes_cipher_fi 61.000s 0.000us 317 350 90.57
aes_ctr_fi 6.000s 62.765us 25 25 100.00
sec_cm_cipher_fsm_sparse 10 10 100.00
aes_fi 6.000s 1163.813us 10 10 100.00
sec_cm_cipher_fsm_redun 595 660 90.15
aes_fi 6.000s 1163.813us 10 10 100.00
aes_control_fi 62.043s 0.000us 268 300 89.33
aes_cipher_fi 61.000s 0.000us 317 350 90.57
sec_cm_cipher_ctr_redun 317 350 90.57
aes_cipher_fi 61.000s 0.000us 317 350 90.57
sec_cm_ctr_fsm_sparse 10 10 100.00
aes_fi 6.000s 1163.813us 10 10 100.00
sec_cm_ctr_fsm_redun 303 335 90.45
aes_fi 6.000s 1163.813us 10 10 100.00
aes_control_fi 62.043s 0.000us 268 300 89.33
aes_ctr_fi 6.000s 62.765us 25 25 100.00
sec_cm_ghash_fsm_sparse 10 10 100.00
aes_fi 6.000s 1163.813us 10 10 100.00
sec_cm_ctrl_sparse 620 685 90.51
aes_fi 6.000s 1163.813us 10 10 100.00
aes_control_fi 62.043s 0.000us 268 300 89.33
aes_cipher_fi 61.000s 0.000us 317 350 90.57
aes_ctr_fi 6.000s 62.765us 25 25 100.00
sec_cm_main_fsm_global_esc 25 25 100.00
aes_alert_reset 15.000s 185.900us 25 25 100.00
sec_cm_main_fsm_local_esc 620 685 90.51
aes_fi 6.000s 1163.813us 10 10 100.00
aes_control_fi 62.043s 0.000us 268 300 89.33
aes_cipher_fi 61.000s 0.000us 317 350 90.57
aes_ctr_fi 6.000s 62.765us 25 25 100.00
sec_cm_cipher_fsm_local_esc 620 685 90.51
aes_fi 6.000s 1163.813us 10 10 100.00
aes_control_fi 62.043s 0.000us 268 300 89.33
aes_cipher_fi 61.000s 0.000us 317 350 90.57
aes_ctr_fi 6.000s 62.765us 25 25 100.00
sec_cm_ctr_fsm_local_esc 303 335 90.45
aes_fi 6.000s 1163.813us 10 10 100.00
aes_control_fi 62.043s 0.000us 268 300 89.33
aes_ctr_fi 6.000s 62.765us 25 25 100.00
sec_cm_ghash_fsm_local_esc 100 100 100.00
aes_ghash_fi 9.000s 553.781us 90 90 100.00
aes_fi 6.000s 1163.813us 10 10 100.00
sec_cm_data_reg_local_esc 595 660 90.15
aes_fi 6.000s 1163.813us 10 10 100.00
aes_control_fi 62.043s 0.000us 268 300 89.33
aes_cipher_fi 61.000s 0.000us 317 350 90.57
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 48.000s 5943.591us 0 10 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 26 test runs
aes_control_fi 45917771591465031627510738450588177709100066003351003300828610363461934851663 None
aes_control_fi 114271714876140331658625783620252549529874332775328107065910065560593801653151 None
aes_control_fi 74756921554669646262581825035341499540323911459344961129624607286609189289153 None
aes_control_fi 63448712486079301075869638088178591715071169303743114614161198687521842381297 None
aes_cipher_fi 95144909799743247467396634564334171858425003497314270722291151611881378968174 None
aes_control_fi 36752743059425446994631833012167263832448393925450806768493821102006533444314 None
aes_cipher_fi 35383330529763146626585057429226067239502821088595146868743576250825889999024 None
aes_control_fi 107288891124006754275786176603975325211530025362353536793519395688912097636994 None
aes_control_fi 39183582411694396561318466559541905554873721321834827014700336514889835237513 None
aes_control_fi 80305214529941117633951187598697219024908635646475342403664170475398476405468 None
aes_cipher_fi 114370034752594269121068601299045141285059578230441590994130610649882527552296 None
aes_cipher_fi 36927769544218938644735367456398481477475834159202851339692314927584363594316 None
aes_cipher_fi 54497744737492503533283185867240759096172781919786793155018095202008405991759 None
aes_control_fi 43381324889021912128191971285437848591960822479985019266453588579290135422663 None
aes_cipher_fi 18563567407871153117440010789109459201047198789274474246256874781155025082456 None
aes_control_fi 43746251209001316456422077449767186124560889373237320855953153417262621633683 None
aes_cipher_fi 106210294107834790672372442821718094167948174274545383835509708184945854237166 None
aes_cipher_fi 31075116992844083890659307147265886224795530361001036602125629930397104176909 None
aes_cipher_fi 88952100926776333132180920697148774693109655826002676542969987031853254830240 None
aes_cipher_fi 114344995061271948221589022782842741695562409894121490016028781904626648626153 None
aes_control_fi 64318459719359711671821075960317283189917136007240514294639966044966266734479 None
aes_control_fi 53830394600164292908751238015020076477315726393891553865013056302567190561775 None
aes_cipher_fi 83626575393222969603240735838236259044421291660887752229022307975753924580437 None
aes_cipher_fi 6423465540014693343198594693362991192373908738658536263255569281714839017600 None
aes_control_fi 30462752996542301985696758893424129984108980140065600669643466469468118107018 None
aes_cipher_fi 23527913582507381752622550693055273255973550823953218244921825246298171463234 None
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 19 test runs
aes_cipher_fi 112396147714196676090490092280642409350013828618959248290615713591994698987436 148
UVM_INFO @ 10028813253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 63879649724722772450400031142165983025161679491786649385266302017351425942165 145
UVM_INFO @ 10013267018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 68095201435353265492958398744978447359165458162435548704591955960203249848751 143
UVM_INFO @ 10008481292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 39620155259524162396314631513575469293242165909784500526948951916773120473431 151
UVM_INFO @ 10007295847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 78620556048858869278560177038127201415181807076369242502272337026826905622703 144
UVM_INFO @ 10025741688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 84685683319256350936610330670010694998178067755635578119985663399581553995460 151
UVM_INFO @ 10019635557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 81645349582049786074704748191471424264304337376581578528622230906950941401487 148
UVM_INFO @ 10019633630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 40709169265571812554556177838486681966845320239682348479345946628108796171128 144
UVM_INFO @ 10014361267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 83134326184171875285384105633807496551954826413775617898246019931910475688806 147
UVM_INFO @ 10008301118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 91511412881280232614703191321233988799629131617795927374808162082165714909267 154
UVM_INFO @ 10019835439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 36218685281290743293162944124257409834703560426175020375694374671813039853182 147
UVM_INFO @ 10206630436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 66479385827146870882386091862496111899559265657499826406585637872074874038214 148
UVM_INFO @ 10010477565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 43627619250242124236074186499804403273199898433111364620579496961339246656856 149
UVM_INFO @ 10049261859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 46836341649240998747651335416823675737084735426202839479846439097221445947059 147
UVM_INFO @ 10013554194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 39059768998411541240562925471528679432261783892298167724620433229996335007217 155
UVM_INFO @ 10013677822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 19785646183409966769832146972410522225904513764083512860050474792122688975065 148
UVM_INFO @ 10066745517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 4091512359511341591774542777720401314525631109657399588855204885967323901640 145
UVM_INFO @ 10047151752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 46143667991628095110523633837438709842942739695958704449247014753692775781151 146
UVM_INFO @ 10012381227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 25864085781359774916707946897906226316301903653592191094928864036896540943207 146
UVM_INFO @ 10014531879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 18 test runs
aes_control_fi 68746694515605146817910452955475379871100470535021484540794110904037250304067 144
UVM_INFO @ 10022290662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 29426371376505287318369483909946360354501638896660662682298873781357626176142 144
UVM_INFO @ 10054905280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 37087645222733385273681500840519064850879626410016901140138469707887261645979 147
UVM_INFO @ 10027119336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 26615190821637295165970420264127847546514368264104330415828150387822822032680 151
UVM_INFO @ 10019913881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 100620213173383455288632785613787627976618103342942710422305554638480070699167 155
UVM_INFO @ 10015104748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 97689039445468558942316561776397656218231829915226542573948619961414564170349 154
UVM_INFO @ 10031266577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 40037545959334253453126770672127760142370539687860967112259836904689901823509 145
UVM_INFO @ 10068430008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 21844002352967778243185591737868005369620269132606100594882792530076073149502 148
UVM_INFO @ 10008660964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 102921082960048901450890565783472521766608805956765079706057303628157360402727 152
UVM_INFO @ 10029824420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 95805508339634425535902018308852143953892314958501604922161766304398581973899 157
UVM_INFO @ 10010894120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 97065369024189943144199134349225875299812150969477006597896983679086453952143 153
UVM_INFO @ 10020836006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 39866367586822923661907594319309569905186323734827013552241145788803405526833 153
UVM_INFO @ 10009993723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 98600330081612176372786948862928783821030765888807371868705310649329795325954 149
UVM_INFO @ 10013857501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 77389582934141755426115782483290564160805630394649132575532555258361543104812 144
UVM_INFO @ 10033979076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 53250344769197869213280989007986394622501217250246557978037754504178043602439 141
UVM_INFO @ 10046318701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 45391679382557561976765576873126652228394364645706897244751257601713016481132 153
UVM_INFO @ 10013095250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 556667335182233932633588557869179956141819596685488513982255381727395358870 152
UVM_INFO @ 10056781645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 111386660085338923854292330835349553350985265615918914262087594752431076849257 155
UVM_INFO @ 10029859283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 9 test runs
aes_stress_all_with_rand_reset 76262753733315249674641655663433566091410668339265087101859643053434047204898 574
UVM_INFO @ 305924857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 55167740041047013246629127621463604358080648193172240644250060131481498292613 1340
UVM_INFO @ 5943591203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 38554545459327314879649248562923254724988628362491130489895713821421790067611 164
UVM_INFO @ 29296170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 89578283223498786120704913078227958352824130416133537984692643130538572577361 171
UVM_INFO @ 80164630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 17078562866320627017163775664827260230553869991772948528394539081745327742023 140
UVM_INFO @ 47030580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 60392886516243051826031224700444565364491639363182335425241433903839652349520 649
UVM_INFO @ 3510225117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 44836577515469651203609544933596388670608988329675719281309294106432355962636 360
UVM_INFO @ 1175259331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 9812745450577157111052934320749676942498521833146981880252574050505649718787 218
UVM_INFO @ 852468740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 31200118517580592942857674144085243775556999462695991480854674832786281656708 413
UVM_INFO @ 375566262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 9 test runs
aes_core_fi 22716857973178084884760399582954056222543572679940572744308184456257733942759 144
UVM_INFO @ 10005153327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 42999288965507905159588959966055043781924930629349237696870144226872325239881 146
UVM_INFO @ 10015359782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 72971693873418765063374460935789788234029151609065714700871870446324728293803 146
UVM_INFO @ 10013777472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 28074373732445997336916140357038524273511326554728412229249610858214389061599 143
UVM_INFO @ 10004729635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 5690949843432134061256815592625926293377345507268829012216885015615902757087 143
UVM_INFO @ 10015038998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 110910076526139531379870818762427114155062417008439854915385449013841002407943 145
UVM_INFO @ 10058636757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 77796627052616759902573967559558821681107846406393565616388627070369177144048 149
UVM_INFO @ 10123326564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 16759749354990310267658188862797746710917126782189775038363995572594813382238 145
UVM_INFO @ 10047643980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 89461570012509261884914541786235722434922819587533944663693051672102266190735 159
UVM_INFO @ 10006480199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) 1 test run
aes_stress_all 15539950358427011732788195414950306446032552916229108681460144968317523608074 380
UVM_INFO @ 4053325873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 21747910412501469627797262483429089640205114277717831110541371476758341990402 492
UVM_INFO @ 2376976527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '*' in file '/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_*/aes_scoreboard.sv' at time * PS + *. 1 test run
aes_config_error 32504588789954726031573706164604861807219836284341520191487524317513113376489 2252
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '748' in file '/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 29248180 PS + 10.
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '748' in file '/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 29248180 PS + 10.
ERROR: Decryption finalizing failed
xmsim: *E,MEMALC: Memory not allocated for actual argument 'predicted_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '748' in file '/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 29248180 PS + 10.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) 1 test run
aes_core_fi 78005376310197545952365805119876539096846506521228867238773227148093323208605 142
UVM_INFO @ 10044852715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:93) [aes_core_fi_vseq] wait timeout occurred! 1 test run
aes_core_fi 98171542538975644025220041541138226248107674481356875479357326725595851933123 141
UVM_INFO @ 10041234423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) 1 test run
aes_cipher_fi 7103491268213433910230009501462206200661554631216407248991524677465235695748 138
UVM_INFO @ 10037105227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) 1 test run
aes_control_fi 18768506287990190213387851227149144117610100925809145892904188494137281773673 138
UVM_INFO @ 10009158897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---