| V1 |
|
100.00% |
| V2 |
|
88.76% |
| V2S |
|
100.00% |
| V3 |
|
40.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 74.850s | 2624.739us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 6.140s | 169.496us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 13.910s | 527.798us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 290.130s | 5639.886us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 343.680s | 38772.752us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 8.460s | 247.231us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 13.910s | 527.798us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 343.680s | 38772.752us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 317.470s | 6691.266us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 82.520s | 2638.791us | 50 | 50 | 100.00 | |
| entropy | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 3419.150s | 66094.051us | 25 | 25 | 100.00 | |
| sig_int_fail | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 105.430s | 3881.981us | 50 | 50 | 100.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 74.850s | 2624.739us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 76.940s | 2708.912us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 85.080s | 1523.436us | 50 | 50 | 100.00 | |
| ping_timeout | 16 | 50 | 32.00 | |||
| alert_handler_ping_timeout | 448.240s | 20779.271us | 16 | 50 | 32.00 | |
| lpg | 97 | 100 | 97.00 | |||
| alert_handler_lpg | 3443.460s | 262552.704us | 50 | 50 | 100.00 | |
| alert_handler_lpg_stub_clk | 3600.134s | 0.000us | 47 | 50 | 94.00 | |
| stress_all | 50 | 50 | 100.00 | |||
| alert_handler_stress_all | 4329.200s | 363315.485us | 50 | 50 | 100.00 | |
| alert_handler_entropy_stress_test | 0 | 20 | 0.00 | |||
| alert_handler_entropy_stress | 33.650s | 3240.694us | 0 | 20 | 0.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 6.620s | 342.617us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.660s | 13.739us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 32.380s | 1691.468us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 32.380s | 1691.468us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 6.140s | 169.496us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 13.910s | 527.798us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 343.680s | 38772.752us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 43.690s | 2664.509us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 6.140s | 169.496us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 13.910s | 527.798us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 343.680s | 38772.752us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 43.690s | 2664.509us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 453.760s | 12798.803us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 453.760s | 12798.803us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 453.760s | 12798.803us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 453.760s | 12798.803us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1318.760s | 16335.220us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 33.290s | 484.017us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 81.990s | 1261.158us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 81.990s | 1261.158us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 453.760s | 12798.803us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 74.850s | 2624.739us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 74.850s | 2624.739us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 74.850s | 2624.739us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 74.850s | 2624.739us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 105.430s | 3881.981us | 50 | 50 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 50 | 50 | 100.00 | |||
| alert_handler_lpg | 3443.460s | 262552.704us | 50 | 50 | 100.00 | |
| sec_cm_esc_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 105.430s | 3881.981us | 50 | 50 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 3419.150s | 66094.051us | 25 | 25 | 100.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 3419.150s | 66094.051us | 25 | 25 | 100.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.290s | 484.017us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.290s | 484.017us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.290s | 484.017us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.290s | 484.017us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.290s | 484.017us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.290s | 484.017us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.290s | 484.017us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.290s | 484.017us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 33.290s | 484.017us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 4 | 10 | 40.00 | |||
| alert_handler_stress_all_with_rand_reset | 478.350s | 5950.397us | 4 | 10 | 40.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 32 test runs | |||
| alert_handler_ping_timeout | 743181388006303251076718289602526106637783649808733854664120340674310558946 | 111 |
UVM_INFO @ 10721591615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 16374244459696296967360030471817377292184562301442035104924323333363539375966 | 84 |
UVM_INFO @ 917548537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 106620514328876855652395392878168693126126761579113673261671506565807129640751 | 96 |
UVM_INFO @ 4667926370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 63842634961714823702753126934812012965128793829574706702245600939230842720850 | 135 |
UVM_INFO @ 28082375629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 94300980123842675419115703042421089151665370575080413700143435996660267865247 | 87 |
UVM_INFO @ 3496985972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 107995145736709022641114478063216667226338076147993322676858964605333359924470 | 84 |
UVM_INFO @ 2094320725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 111854816419850785203497170043902088709344007454634881748706924185992600422693 | 108 |
UVM_INFO @ 4323973807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 95727339854194315273273905408093628786421698879378935777261756320065371980769 | 105 |
UVM_INFO @ 4558606616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 39600548983882881327514648038111014945407817352967556363112133313725406244663 | 99 |
UVM_INFO @ 10741756313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 64774567482597727149991481660285622706685193656482377944307394830203596956813 | 141 |
UVM_INFO @ 18091134128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 69548401441679238311025263736343695095852883109265038322558479766793585846408 | 102 |
UVM_INFO @ 16400790149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 77890118006963402022101654769711674545749810576224804986104710269147313370952 | 102 |
UVM_INFO @ 7100425920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 67129706341083288373064180280925976496487958804744460078913121284256533658533 | 90 |
UVM_INFO @ 7954822214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 73010588607544416826688335902823818903162775577667250220661710038226579004707 | 90 |
UVM_INFO @ 3314442281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 45454599376360625998921188169302155069266927627265853002686393032191627743772 | 117 |
UVM_INFO @ 9977945667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 80819358021057819196053633186760018238320297640153236029132883212875892131543 | 144 |
UVM_INFO @ 39826683279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 101063116861995079146985388225969435934411215934042770687024049994473500276256 | 96 |
UVM_INFO @ 2189493791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 109393283392194803009515558871073129225850653287879197024954426575938940261225 | 113 |
UVM_INFO @ 10173647828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 43580286388770792244056763446662000632531807655138579660271436501242601815030 | 90 |
UVM_INFO @ 7814280006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 42388702921444421227420290473296509203243409650310215191011856146072564064943 | 104 |
UVM_INFO @ 4283612696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 6405746998713730881528585479640060018109718438528067829437149904758993853417 | 93 |
UVM_INFO @ 6625334302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 54146045858992827882152348490948803795350235414519526623882076139436142903527 | 135 |
UVM_INFO @ 53703620982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 13055815141438326579653489359548249483925838933805686198035999061330663097900 | 96 |
UVM_INFO @ 8445026455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 73087483914976967102975460887643274581533815838955661771279461315815636778206 | 117 |
UVM_INFO @ 4333488555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 111638331625747699139056649926792496846938745397274451755429047411887091667548 | 87 |
UVM_INFO @ 8866283733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 42152025458065228248917090590871147471755769179916505910728947516893537639658 | 118 |
UVM_INFO @ 5069527618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 100730250959134964633221380487155598453034262594974281481389372883120971126831 | 87 |
UVM_INFO @ 1567939752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 3289296118605554480376799785335462341109855564834883310634445383296873586863 | 96 |
UVM_INFO @ 10504554159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 72369751285348882999101838056724390087824184649713905727542708692619443651982 | 142 |
UVM_INFO @ 37108708055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 43675696744857914148067592320522638958547626842986170920206006270698866639212 | 93 |
UVM_INFO @ 2182657159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 73980115581307686009847692795434453371909925085737010258323112125722237373717 | 106 |
UVM_INFO @ 16814555020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 50197969785063912538483028332976489765431030541102449562065710213491647234744 | 84 |
UVM_INFO @ 2238816590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 20 test runs | |||
| alert_handler_entropy_stress | 22725737936376086990616240001251944579910564755777910388516885942374418073581 | 112 |
UVM_INFO @ 792269929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 75613200947338679128836169305923584408062782203002129229363477697046510029986 | 202 |
UVM_INFO @ 5309725476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 86003540304133970560674503202545986590011960892571895832576791494146585862590 | 176 |
UVM_INFO @ 1155841863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 54008716546412669947909767519992563613147436632392702643334879666800367837896 | 158 |
UVM_INFO @ 209461741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 45171380339187924652876796540628673705224144054825567872248966768837933617106 | 160 |
UVM_INFO @ 190950788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 54088462603845952530139429023347048204787608579775353665256326084891155234878 | 216 |
UVM_INFO @ 98290853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 68742761747510271691693521960260712400184524959108986748924882354532762054372 | 162 |
UVM_INFO @ 703267268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 67255332421155429085876894427696566833711165916415763497608031529711100628561 | 194 |
UVM_INFO @ 399923772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 6547391012208398991026311682110310409501282161999933685209991913066271181624 | 218 |
UVM_INFO @ 1638065249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 11273745230246227869939501151884828595937529956728860853024517238737029747659 | 228 |
UVM_INFO @ 187253244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 113480693324157241378547196243876641595172442984779606037748004909826347900928 | 166 |
UVM_INFO @ 637382425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 64228437777103036408082607038514270474404804101931305398842158194538262137492 | 164 |
UVM_INFO @ 352055820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 60976897343884779060627591212038389172047896999756292166151476633725019078265 | 224 |
UVM_INFO @ 1427192657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 79271547956571434191040394934628510389718740370193837824204082186479362632727 | 228 |
UVM_INFO @ 221846511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 107189232967134214055858374091708699310188166623429507195169916404344639694991 | 218 |
UVM_INFO @ 136472176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| alert_handler_entropy_stress | 103912568633972530469636394427456340835304286616997359291783255043310129141701 | 184 |
UVM_INFO @ 629025698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_entropy_stress | 59501381456445108791154055413822930595866189016111836118394060397408301348549 | 196 |
UVM_INFO @ 182954552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_entropy_stress | 16202964232200494826663465964217298898246971890707132308828452532930357685110 | 202 |
UVM_INFO @ 97849992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_entropy_stress | 108840882146994785377546734056663743411268038905936453702039556048620856523177 | 194 |
UVM_INFO @ 3240694462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_entropy_stress | 66844986116751592959563622883657431907609832587919550465550572212416863617866 | 206 |
UVM_INFO @ 410920389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 5 test runs | |||
| alert_handler_stress_all_with_rand_reset | 52080788072221456927586270910882218222874696031860910758847553132013846364232 | 83 |
UVM_INFO @ 111302375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_stress_all_with_rand_reset | 10508701533045451107835912159270080920607374761152485922177239171826271163947 | 124 |
UVM_INFO @ 7065282200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_stress_all_with_rand_reset | 51520081991429524588709063398830221953015715340880769275400456933620736149185 | 94 |
UVM_INFO @ 396685886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_stress_all_with_rand_reset | 82041116878179345520824257431526556684172839017925987318358994605920712920777 | 87 |
UVM_INFO @ 1301656948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_stress_all_with_rand_reset | 74566468349936202316376590333527960873810705250666615410068104491090159551677 | 101 |
UVM_INFO @ 763267052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| Job timed out after * minutes | 2 test runs | |||
| alert_handler_lpg_stub_clk | 32145262759318071863194270876927154285600635924927169639858697051912486843058 | None | ||
| alert_handler_lpg_stub_clk | 24370958543508361109610746828435624237245032866316971572149901531467002836305 | None | ||
| UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 2 test runs | |||
| alert_handler_ping_timeout | 112905647008006237289567315861225494559150471137061353222705917518480585161693 | 80 |
UVM_INFO @ 155062044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_ping_timeout | 924974648850838248681488874877896703012015344580332622173623455569041017109 | 81 |
UVM_INFO @ 1247604380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (cip_base_vseq.sv:1199) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. | 1 test run | |||
| alert_handler_stress_all_with_rand_reset | 90092110065212142302354584667286858824892708343242618435975102653150907214321 | 82 |
UVM_INFO @ 242859295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 1 test run | |||
| alert_handler_lpg_stub_clk | 75555712927289193298445275218286752794887113460159413862038650158682950595186 | 80 |
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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