Simulation Results

Simulation Results: clkmgr

06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
77.59 %

code
69.18 %

assert
89.88 %

func
73.71 %

line
81.76 %

branch
86.53 %

cond
79.88 %

toggle
97.74 %

FSM
0.00 %

Validation stages

V1		69.57%
V2		69.23%
V2S		29.52%
V3		0.00%

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	2.240s	84.011us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.270s	22.621us	1	1	100.00
csr_rw				2	5	40.00
	clkmgr_csr_rw	1.170s	16.685us	2	5	40.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	2.700s	78.715us	0	1	0.00
csr_aliasing				1	1	100.00
	clkmgr_csr_aliasing	1.860s	38.068us	1	1	100.00
csr_mem_rw_with_rand_reset				2	5	40.00
	clkmgr_csr_mem_rw_with_rand_reset	3.920s	293.883us	2	5	40.00
regwen_csr_and_corresponding_lockable_csr				3	6	50.00
	clkmgr_csr_rw	1.170s	16.685us	2	5	40.00
	clkmgr_csr_aliasing	1.860s	38.068us	1	1	100.00

81/117 passed

69.23 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	3.190s	150.708us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	3.250s	147.420us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	1.660s	52.946us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	2.240s	84.011us	10	10	100.00
frequency				0	10	0.00
	clkmgr_frequency	1.150s	14.842us	0	10	0.00
frequency_timeout				0	10	0.00
	clkmgr_frequency_timeout	1.080s	12.517us	0	10	0.00
frequency_overflow				0	10	0.00
	clkmgr_frequency	1.150s	14.842us	0	10	0.00
stress_all				2	10	20.00
	clkmgr_stress_all	5.040s	255.294us	2	10	20.00
alert_test				10	10	100.00
	clkmgr_alert_test	3.590s	217.214us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	10.360s	748.152us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	10.360s	748.152us	25	25	100.00
tl_d_outstanding_access				4	12	33.33
	clkmgr_csr_hw_reset	1.270s	22.621us	1	1	100.00
	clkmgr_csr_rw	1.170s	16.685us	2	5	40.00
	clkmgr_csr_aliasing	1.860s	38.068us	1	1	100.00
	clkmgr_same_csr_outstanding	1.820s	62.718us	0	5	0.00
tl_d_partial_access				4	12	33.33
	clkmgr_csr_hw_reset	1.270s	22.621us	1	1	100.00
	clkmgr_csr_rw	1.170s	16.685us	2	5	40.00
	clkmgr_csr_aliasing	1.860s	38.068us	1	1	100.00
	clkmgr_same_csr_outstanding	1.820s	62.718us	0	5	0.00

V2S

31/105 passed

29.52 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				0	30	0.00
	clkmgr_sec_cm	136.030s	10082.570us	0	5	0.00
	clkmgr_tl_intg_err	2.240s	72.636us	0	25	0.00
shadow_reg_update_error				19	20	95.00
	clkmgr_shadow_reg_errors	2395.700s	200000.000us	19	20	95.00
shadow_reg_read_clear_staged_value				19	20	95.00
	clkmgr_shadow_reg_errors	2395.700s	200000.000us	19	20	95.00
shadow_reg_storage_error				19	20	95.00
	clkmgr_shadow_reg_errors	2395.700s	200000.000us	19	20	95.00
shadowed_reset_glitch				19	20	95.00
	clkmgr_shadow_reg_errors	2395.700s	200000.000us	19	20	95.00
shadow_reg_update_error_with_csr_rw				0	20	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	1.330s	29.427us	0	20	0.00
sec_cm_bus_integrity				0	25	0.00
	clkmgr_tl_intg_err	2.240s	72.636us	0	25	0.00
sec_cm_meas_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency	1.150s	14.842us	0	10	0.00
sec_cm_timeout_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency_timeout	1.080s	12.517us	0	10	0.00
sec_cm_meas_config_shadow				19	20	95.00
	clkmgr_shadow_reg_errors	2395.700s	200000.000us	19	20	95.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	5.130s	278.880us	10	10	100.00
sec_cm_jitter_config_mubi				2	5	40.00
	clkmgr_csr_rw	1.170s	16.685us	2	5	40.00
sec_cm_idle_ctr_redun				0	5	0.00
	clkmgr_sec_cm	136.030s	10082.570us	0	5	0.00
sec_cm_meas_config_regwen				2	5	40.00
	clkmgr_csr_rw	1.170s	16.685us	2	5	40.00
sec_cm_clk_ctrl_config_regwen				2	5	40.00
	clkmgr_csr_rw	1.170s	16.685us	2	5	40.00
prim_count_check				0	5	0.00
	clkmgr_sec_cm	136.030s	10082.570us	0	5	0.00

0/20 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
regwen				10
	clkmgr_regwen	1.340s	32.427us	10
stress_all_with_rand_reset				10
	clkmgr_stress_all_with_rand_reset	71.530s	3968.293us	10

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:				31 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	101548975026844992607155844349565370900845272148040182432559664803680940260555	75	UVM_INFO @ 5992744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	77326918069698091739416522332880085990273063520906364751051709301095553541052	75	UVM_INFO @ 4434223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	83777489442402300538645621612830196362847109598623034474542056001735286558647	75	UVM_INFO @ 11915395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	4621648120812477689310114198150851784737854082313605923633492567627162761706	97	UVM_INFO @ 25491120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	64403576590415270223547439837540031520470263708958359465497895207312969777661	75	UVM_INFO @ 2991016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	30548231396968802471998147904087935313258458602416239266787670639196322075867	85	UVM_INFO @ 3140253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	30793504412119752741660562284746394933223516063284989894221012938019967078993	82	UVM_INFO @ 61792049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	2771674797979739837728274699475480290591495814656041929967530593476022195002	82	UVM_INFO @ 5735637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	10194510803131284983766263891287088656276916952685100322773625578954699572335	75	UVM_INFO @ 2432201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	47340480937945534913457270726824317713754995355434087530594985974536831468645	82	UVM_INFO @ 21105758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	23552911064001796853083189725607925850238791176517451523684468426077450772117	75	UVM_INFO @ 16904410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	110065075329271415571699007923128099774239796894832132258539264682372439550965	75	UVM_INFO @ 13589683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	63385489910653450279323018479385125029884845379524199243706884423738466209809	78	UVM_INFO @ 12140330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	19127030661204341243519477265023383735210839363142349535369418926711722630567	75	UVM_INFO @ 8056273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	84258114982466217260141770121787908024393327303848421932351823566018301748414	75	UVM_INFO @ 2407719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	98732680995993556473291038626644727616626115982368792946612547017740676444470	75	UVM_INFO @ 7194417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	72188174692599380909973735322344419501244848298054276361705679720685985297685	115	UVM_INFO @ 72635607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	56745694033537467644719021269350421314432587398068869583047009606588177775295	89	UVM_INFO @ 12254830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	3365010021347059345806523368366144726592432483072710500864430862737694170890	75	UVM_INFO @ 10231281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	85154013785508414701352532007671315978600681110648702909008025863776698543625	75	UVM_INFO @ 9051244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	109616158743393806500604864876335364662071839837974115216933177727608249970744	98	UVM_INFO @ 18465744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	36325429011146315090495777627901545954977831192145183163957717242404185004865	75	UVM_INFO @ 6767355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	66239701559537595806322449796509896278100272698779773797772121057429182691184	75	UVM_INFO @ 16110057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	64517873789511702328579511101996748955080012266451334094460979367885748311578	75	UVM_INFO @ 6874422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	52307286837017731813371481311986541242525775589059404931830533552277995912262	82	UVM_INFO @ 4073352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	67488035598821689726829444623510775368984805435993179235314843665379321327994	75	UVM_INFO @ 3532689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	67486353980780985023613120646018945401755914467580822283549769919595875937359	75	UVM_INFO @ 2845207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	68793787953345979794659254853016739000189169549653954337620303611533210872207	86	UVM_INFO @ 12967024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	86699742969490581515304754090705556602037250053403523058686386637854074848845	83	UVM_INFO @ 9873037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	17466690278169546988809673629713422856700790007322059450075989392701914276128	82	UVM_INFO @ 2243478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	56987259162703333496409206433458792150998197233744518324412197655673308522981	75	UVM_INFO @ 1596436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b				23 test runs
	clkmgr_frequency_timeout	5496213013565361028309337924628680969939521820001401588052304307117788978361	78	UVM_INFO @ 2837185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	79571990828030786760523876449619308665106483165638797168532792220491311590317	78	UVM_INFO @ 10057873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	7551237004322274995526155143507364762273606607237439637644254803067875375260	143	UVM_INFO @ 75160691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	93564700051921172637408114670565869342551317642338308463436787828321722036089	78	UVM_INFO @ 255294042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	64171981751958603326144903206290691212196144847687975148595048749040366016087	78	UVM_INFO @ 3738528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	53207867818686691300716533199113880105781712322256830550345425261158881956541	78	UVM_INFO @ 6169510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	62397047141733163658831292243473986649601681702627307131758699439115774217669	79	UVM_INFO @ 54120653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	85735012538507167788175526665438398383261595631767270238103632294749978864225	78	UVM_INFO @ 9416935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	91318868088830036995176169015348596082715091078700886980761578663698737877634	78	UVM_INFO @ 2945349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	63124707709875696811367042194588642396361488142384034912735440078946567555779	79	UVM_INFO @ 2991238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	4856811380245183708757695548986218894553741380192548374081070330447607412437	78	UVM_INFO @ 2920357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	55453574574302267948978728521615981337707655089179069118402650353927330986658	79	UVM_INFO @ 4787268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	41488759865203756138370796282384155920265869403307256031166321278121672880468	102	UVM_INFO @ 115534012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	86741433824349717601169952216424057011402895213469830888795235650574984941105	78	UVM_INFO @ 12500811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	51067423900353860506440545207088785859335950423763598954000473963292671237666	173	UVM_INFO @ 117982415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	31962048914363972643694271556015940539607602441643583896831266002532109428102	77	UVM_INFO @ 6585860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	10127430102278135045068536687642923843362029442836664419413395521415672438404	127	UVM_INFO @ 107892664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	105862834721902076375951179454518652847428461814978557200829058541221478219491	166	UVM_INFO @ 224680736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	29415780869076939148833094239261176562780757539283054812278906185852725912381	77	UVM_INFO @ 12517024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	73095543574063579755680218199432067318728228556029070207477524057083235098448	89	UVM_INFO @ 85725594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	62646978375324957010236035608423896712199935949725382579049282385084818359853	77	UVM_INFO @ 9950371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	60996216855051231571967089292932380128497891761380466837056085733358843789663	78	UVM_INFO @ 4979996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	49172004081643862377764990562724451714925455038111597757572628497464824444603	115	UVM_INFO @ 30218901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:				20 test runs
	clkmgr_tl_intg_err	49451127185037118347999969289426364478100322700869149174953721770714435107053	108	UVM_INFO @ 18721082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	104984651933046742080857428604287836046438688702412509590302215574281841037490	76	UVM_INFO @ 2512559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	6842107949841931691769672007918347041675855131725692945429026772277878138793	75	UVM_INFO @ 2133017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	50966044113346034748864445361548184797051406464546423986639762424554015644359	75	UVM_INFO @ 13456508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	28296340256008744147739521735925074457344305208777077926003147591948674704446	75	UVM_INFO @ 4240164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	64648693352911887690169249705222970005504192589258262969861032646578029831003	75	UVM_INFO @ 16858811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	98804932863046195202027465987128262774928560347832750587917729132570097051345	82	UVM_INFO @ 29426268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	72531884944862356316929755915882671429718004774223210518257725729141815510387	75	UVM_INFO @ 29426592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	71202488645376884165445131914448025425213395887321297604502125699873084221145	93	UVM_INFO @ 36345908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	106621021579927105543320770142331235469773436966736760138310119978112653740542	82	UVM_INFO @ 2952356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	83012432131821804672138967795830546702364712143603620428878563093383625878537	75	UVM_INFO @ 16259565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	31353442474069495306119282167042495270156328631524139256378019792586888197324	93	UVM_INFO @ 30692101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	100757788725921241683367607270325428128801875360080865352215530163832049955706	75	UVM_INFO @ 14255225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	6626416582885311689113791900583448911781114713475574098526037213404918345301	85	UVM_INFO @ 9106263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	45934420351777010244428609106538388244644524940354905936003743460276447378166	75	UVM_INFO @ 1833424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	10448529949692461970782233104765282570768062331583471557356792769392156899313	89	UVM_INFO @ 33457465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	59494552738650386400498523011686520841712959904502678112858564881868163334597	75	UVM_INFO @ 8413554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	75761737538704674797167307397048456007145728516525973978976228272865521910519	75	UVM_INFO @ 10765045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	115513276388825807941338045628270161488624151950047772463506858204682723161318	78	UVM_INFO @ 2903713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	82968365442205769759192519997822425515289175232125390365176292255940519502946	109	UVM_INFO @ 53328273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b				15 test runs
	clkmgr_frequency	97384292713441610730510566893488295610764322686404687195889272009455970668521	75	UVM_INFO @ 6700523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	3691443951278198305810704482782812564177258441129429294977013644859346309796	192	UVM_INFO @ 3968292805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	39669920147702423199285312695667324312857454282421540396047403591313253382218	77	UVM_INFO @ 15757839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	33937322893451769301152653687997192147552366346732990974375696183118618763056	76	UVM_INFO @ 5105655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	13701097382185794800776131401755728917688914635575833281131953507240556363668	76	UVM_INFO @ 6749615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	28331749805671179587701194534609129893685294051348817959934944916075481652910	77	UVM_INFO @ 16552590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	95911368219802883218666589251642121583858065352080806969570191237534316932491	75	UVM_INFO @ 4002816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	3711220459212421868069852431707726336699286319289190299883066430717564035243	76	UVM_INFO @ 18087689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	100067048546894123054872430290165810586776222035425879918662316892882568233551	76	UVM_INFO @ 10560825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	115645076464855353891198537867242302084794215772009225750268721251151021237097	75	UVM_INFO @ 14842383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	38499002091813680869915564575491653334278641579842422439160584841710149628074	77	UVM_INFO @ 9966879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	26509040339990875353197812142369171265464806216050401534631329003566791976365	76	UVM_INFO @ 3616394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	113559590459753390950885613693678366807025045064100130862572707660536406465952	75	UVM_INFO @ 9122080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	65193438285801151728035297892421599905191058764157343318374281101210865273589	75	UVM_INFO @ 8470899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	43964286802649704895730091942123839200038114021118785244384900355526024097361	148	UVM_INFO @ 150853544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en				6 test runs
	clkmgr_regwen	105478080568904041472946547668310850716674797494557468962315709957593729781037	74	UVM_INFO @ 3186017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	12145568725473022861217762575727491769469316416699331707996457562520390116610	74	UVM_INFO @ 10657508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	25481744572354718864310856731139266112301567443190891713767465883437830512843	74	UVM_INFO @ 10699966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	105640724011799179702252744780513580368021955088405900855693796162671897167414	74	UVM_INFO @ 7422715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	36047901163950258341877915170180089565775986596144472199909639153736372620081	74	UVM_INFO @ 2761585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	101642178765577032386622400436185026697672627492175258358128050824262776058013	74	UVM_INFO @ 3471591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				5 test runs
	clkmgr_same_csr_outstanding	70005833129283156245359257410299864501470508095137678581792935438355116458668	76	UVM_INFO @ 36564373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	48318195400008088446287367024627682727715766643465553122070744662544816357330	76	UVM_INFO @ 29088477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	12173063545546775270559533848761726405794673561902249277706651129952065872189	75	UVM_INFO @ 1684133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	104344388278341489976685364041259741668426032939935425423774567922339118588285	75	UVM_INFO @ 8604680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	33720030413625743363488082116504702873226528581432247064332788608934268824543	75	UVM_INFO @ 62717627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed				3 test runs
	clkmgr_regwen	2678887697674792174523664845853140583484858212755834372383739917911567307843	74	UVM_INFO @ 3820250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	74773391478725588328257692569732441419149304976167966890775377770965719393798	74	UVM_INFO @ 2896813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	67757685394126262101660878928105841828909423464991028546536939137919925317909	74	UVM_INFO @ 32426799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault				3 test runs
	clkmgr_sec_cm	19694258077192617498011118246872927073639343056723107142056786913576601181755	110	UVM_INFO @ 10082570496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	67232448932762588109301490104992692110519247320373175837342874910020029661669	88	UVM_INFO @ 10025033926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	11974524521871372352434443656143591194205276964403187700619935360743077069404	154	UVM_INFO @ 10110673379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				2 test runs
	clkmgr_sec_cm	35607429207346443072306133069479325089037114531682899291315041796408607647271	184	UVM_INFO @ 239330514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	98821422381430108392522104843625121406729957160497752462283769204936580116054	79	UVM_INFO @ 5427944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:				1 test run
	clkmgr_csr_bit_bash	21329755971754767964459955179559173261816608004824194645515130608215901507634	75	UVM_INFO @ 78715325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en				1 test run
	clkmgr_regwen	68760194132500752772144298216833912859847152248711460713194343813806089085400	74	UVM_INFO @ 3741559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	clkmgr_shadow_reg_errors	100703960586542735425101065116910588673333965443551860792549418260059334660641	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---