Simulation Results

Simulation Results: csrng

06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.59 %

code
96.12 %

assert
97.16 %

func
90.50 %

block
98.43 %

line
99.47 %

branch
96.13 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		97.93%
V2S		98.52%
V3		0.00%

38/38 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				25	25	100.00
	csrng_smoke	3.000s	23.356us	25	25	100.00
csr_hw_reset				1	1	100.00
	csrng_csr_hw_reset	30.000s	18.301us	1	1	100.00
csr_rw				5	5	100.00
	csrng_csr_rw	30.000s	31.653us	5	5	100.00
csr_bit_bash				1	1	100.00
	csrng_csr_bit_bash	42.000s	464.868us	1	1	100.00
csr_aliasing				1	1	100.00
	csrng_csr_aliasing	31.000s	68.198us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	csrng_csr_mem_rw_with_rand_reset	30.000s	23.297us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	csrng_csr_rw	30.000s	31.653us	5	5	100.00
	csrng_csr_aliasing	31.000s	68.198us	1	1	100.00

1280/1307 passed

97.93 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	20.000s	1045.947us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	46.000s	3192.616us	500	500	100.00
err				499	500	99.80
	csrng_err	191.000s	10011.234us	499	500	99.80
cmds				1	25	4.00
	csrng_cmds	2740.000s	200000.000us	1	25	4.00
life cycle				1	25	4.00
	csrng_cmds	2740.000s	200000.000us	1	25	4.00
stress_all				23	25	92.00
	csrng_stress_all	970.000s	68989.608us	23	25	92.00
intr_test				10	10	100.00
	csrng_intr_test	5.000s	22.737us	10	10	100.00
alert_test				10	10	100.00
	csrng_alert_test	30.000s	27.558us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	csrng_tl_errors	16.000s	1426.904us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	csrng_tl_errors	16.000s	1426.904us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	csrng_csr_hw_reset	30.000s	18.301us	1	1	100.00
	csrng_csr_rw	30.000s	31.653us	5	5	100.00
	csrng_csr_aliasing	31.000s	68.198us	1	1	100.00
	csrng_same_csr_outstanding	5.000s	99.473us	5	5	100.00
tl_d_partial_access				12	12	100.00
	csrng_csr_hw_reset	30.000s	18.301us	1	1	100.00
	csrng_csr_rw	30.000s	31.653us	5	5	100.00
	csrng_csr_aliasing	31.000s	68.198us	1	1	100.00
	csrng_same_csr_outstanding	5.000s	99.473us	5	5	100.00

V2S

1266/1285 passed

98.52 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	csrng_sec_cm	8.000s	432.221us	5	5	100.00
	csrng_tl_intg_err	24.000s	2014.791us	25	25	100.00
sec_cm_config_regwen				14	30	46.67
	csrng_regwen	3.000s	29.638us	9	25	36.00
	csrng_csr_rw	30.000s	31.653us	5	5	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	46.000s	3192.616us	500	500	100.00
sec_cm_intersig_mubi				23	25	92.00
	csrng_stress_all	970.000s	68989.608us	23	25	92.00
sec_cm_main_sm_fsm_sparse				704	705	99.86
	csrng_intr	20.000s	1045.947us	200	200	100.00
	csrng_err	191.000s	10011.234us	499	500	99.80
	csrng_sec_cm	8.000s	432.221us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				704	705	99.86
	csrng_intr	20.000s	1045.947us	200	200	100.00
	csrng_err	191.000s	10011.234us	499	500	99.80
	csrng_sec_cm	8.000s	432.221us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				704	705	99.86
	csrng_intr	20.000s	1045.947us	200	200	100.00
	csrng_err	191.000s	10011.234us	499	500	99.80
	csrng_sec_cm	8.000s	432.221us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				704	705	99.86
	csrng_intr	20.000s	1045.947us	200	200	100.00
	csrng_err	191.000s	10011.234us	499	500	99.80
	csrng_sec_cm	8.000s	432.221us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				704	705	99.86
	csrng_intr	20.000s	1045.947us	200	200	100.00
	csrng_err	191.000s	10011.234us	499	500	99.80
	csrng_sec_cm	8.000s	432.221us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	46.000s	3192.616us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				699	700	99.86
	csrng_intr	20.000s	1045.947us	200	200	100.00
	csrng_err	191.000s	10011.234us	499	500	99.80
sec_cm_constants_lc_gated				23	25	92.00
	csrng_stress_all	970.000s	68989.608us	23	25	92.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	46.000s	3192.616us	500	500	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	csrng_tl_intg_err	24.000s	2014.791us	25	25	100.00
sec_cm_aes_cipher_fsm_sparse				704	705	99.86
	csrng_intr	20.000s	1045.947us	200	200	100.00
	csrng_err	191.000s	10011.234us	499	500	99.80
	csrng_sec_cm	8.000s	432.221us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				699	700	99.86
	csrng_intr	20.000s	1045.947us	200	200	100.00
	csrng_err	191.000s	10011.234us	499	500	99.80
sec_cm_aes_cipher_ctrl_sparse				699	700	99.86
	csrng_intr	20.000s	1045.947us	200	200	100.00
	csrng_err	191.000s	10011.234us	499	500	99.80
sec_cm_aes_cipher_fsm_local_esc				699	700	99.86
	csrng_intr	20.000s	1045.947us	200	200	100.00
	csrng_err	191.000s	10011.234us	499	500	99.80
sec_cm_aes_cipher_ctr_redun				704	705	99.86
	csrng_intr	20.000s	1045.947us	200	200	100.00
	csrng_err	191.000s	10011.234us	499	500	99.80
	csrng_sec_cm	8.000s	432.221us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				699	700	99.86
	csrng_intr	20.000s	1045.947us	200	200	100.00
	csrng_err	191.000s	10011.234us	499	500	99.80

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	3601.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				21 test runs
	csrng_cmds	514871875313646260600234380820682924161013896944655531273846465948678263718	100	UVM_INFO @ 94310698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	107224640184892919389622287469258070344872731879492561089166265384439267767516	100	UVM_INFO @ 351920509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	54734499901566400947314871278041538921549749594218501604946626388567663096488	100	UVM_INFO @ 65430093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	61720453159749037038904915942953440868345878909482241053055740461915287820845	100	UVM_INFO @ 160837002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	60364996295603186953688301957524426473049101031764486191384706829614930024830	100	UVM_INFO @ 101000762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	50463476006538790865787508553276347800133554897952389175752805858535561952182	100	UVM_INFO @ 88127964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	20566875772861210923977932668369954858796953314061752035976684571842993711853	100	UVM_INFO @ 212820243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	21197671389641264173737552611311747775480412678244940283099890638139790030731	100	UVM_INFO @ 81801571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	89744053810001962256302123678267556939731579265231134167708081116007872020539	100	UVM_INFO @ 114314941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	23806684887016279926739543806866365194998371970098366267934465328952978491928	100	UVM_INFO @ 95310597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	48341803731729101611003258525450238738532657612814300939642575882985221559286	100	UVM_INFO @ 197374354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	67879007106682247056828842327049512570069602447969663547283147148708882458562	100	UVM_INFO @ 18381028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	38795516990055730555203939180846303656785147824545865707338841305466589906897	120	UVM_INFO @ 358697568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	30536938763880290202283773588365002971072104119547607452421848441575020603441	110	UVM_INFO @ 291238415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	91295954285027213864015115863526542013156285079557663918358745865957033519314	100	UVM_INFO @ 56785398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	46701072199781894061775083731806009933435784012038569164129047790021774455039	100	UVM_INFO @ 16423258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	73393720017687018052210625314539084864925231903800973233309368660995632184506	100	UVM_INFO @ 78263142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	3296894731678846505211435597096256455420202405280702837876080229463230470878	100	UVM_INFO @ 41097189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	19505231439486994778271453456844320077077102516317164216654708003012595490955	110	UVM_INFO @ 169581613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	24323278409236807652902186837096724825891545186177913416284119683576806735302	100	UVM_INFO @ 37552070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	114977629436924616746556784761647063528112835468905177013649087838794838435369	110	UVM_INFO @ 217267998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE				14 test runs
	csrng_regwen	35787291014006116626451575935576782096898759447920630656516386024462796470893	99	UVM_INFO @ 3450002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	96304212373691929777557719840556987137039912080167890490531796966534590687304	99	UVM_INFO @ 2329044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	18709585645503768840294146829848680204634046589493655851680916613790020865027	99	UVM_INFO @ 9911018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	99653122813975045897000327763984027172365254021368802348689567462466823487899	99	UVM_INFO @ 6347129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	99828970920610260415846514860036687243603161210881678072140220092798349322272	99	UVM_INFO @ 4288797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	48581435345320263274969110286281707116858531627345381498782179744263964954555	99	UVM_INFO @ 1028084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	99915486632820613614568827690801329742365648995193121981347606899341873408573	99	UVM_INFO @ 10372846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	36252999699581669935470365834303327705288340936421645221020902383880462344260	99	UVM_INFO @ 1984746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	95093576990065548594341835450990626794032242752476525298437988342696466812254	99	UVM_INFO @ 2941834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	11254654891909240233571025341805913699111044726347695354840050130432915831218	99	UVM_INFO @ 4492728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	96623103205020197359513582692024598455628335819198650217063159358709576655094	99	UVM_INFO @ 4625290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	2283362018410926690267742280955590819443342357183887700988218121078861093053	99	UVM_INFO @ 2592073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	102407883714150195395772718230326141627838654307994897820376410209785427529613	99	UVM_INFO @ 4622905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	2885413915514855552082503761516943570107111476267593268397368349264574434784	99	UVM_INFO @ 2128571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				6 test runs
	csrng_stress_all_with_rand_reset	90922278205085653516510122169774943185976759798990624131909113029678144156917	None
	csrng_stress_all_with_rand_reset	57341757901731482473905030752164573252810079330660526668864145442487100443085	None
	csrng_stress_all_with_rand_reset	90117852324432747935938290332462127728480393537494979781109423998301838434998	None
	csrng_stress_all_with_rand_reset	17845756663193316664550852712800193874734691862711000085710775306769274495124	None
	csrng_stress_all_with_rand_reset	33395068420122645206450002008537544185087629950708967833119240033869700862240	None
	csrng_stress_all_with_rand_reset	37900397976744484532233544557014355771419839415834616181305917886864672945062	None
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				5 test runs
	csrng_stress_all_with_rand_reset	38891083116714713903447406677155595946115326623261358223190945219530383397150	131	UVM_INFO @ 1976401584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	9808766056995279199181204571776817177985185818779816233587356315231296656573	105	UVM_INFO @ 50423694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	27026278380486781230759086270144842557670281649941387911612006047758992244061	107	UVM_INFO @ 115112097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	62557172920221644715884760042630236916918710344128516433411583824114456267440	117	UVM_INFO @ 6786533747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	24456170528986813960877530370298584832802986042718746229338119152316763019855	114	UVM_INFO @ 2016422618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE				2 test runs
	csrng_regwen	114970596046307026601628163112312222782485382585397022104853347748676898183833	99	UVM_INFO @ 21123082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	43829068197580292910485380029270865119032207414723890066689031176436015716967	99	UVM_INFO @ 12774906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_env_cfg.sv:348) [cfg] Check failed csr_reseed_counter == reseed_counter[app] (* [] vs [*])				1 test run
	csrng_stress_all_with_rand_reset	45504175673003976841640772677794041883103876558993682427488645023991649000945	104	UVM_INFO @ 89763012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:304) [scoreboard] Check failed cmd_sts[SW_APP] == item.d_data[:] (* [] vs [*])				1 test run
	csrng_cmds	69576810168815002389816303352785135408205316190562756516993065447758302955942	108	UVM_INFO @ 11096618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits				1 test run
	csrng_cmds	63041977240074428333448690913767461184531705824546260122403263755706280114461	103	UVM_INFO @ 230865305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	csrng_cmds	87800158701961283841424342402429301796392872033913956342415630882237513329764	109	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [csrng_err_vseq] wait timeout occurred!				1 test run
	csrng_err	112408666265516346563481160434854450493682997692404157291574299145881331270340	99	UVM_INFO @ 10011233600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---