Simulation Results: edn/edn0

 
06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.23 %
  • code
  • 95.28 %
  • assert
  • 98.67 %
  • func
  • 58.74 %
  • block
  • 96.95 %
  • line
  • 98.68 %
  • branch
  • 93.23 %
  • toggle
  • 89.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.35%
V2S
100.00%
V3
93.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 2.000s 24.184us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 35.014us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.000s 42.151us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 61.239us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 21.033us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 3.000s 45.197us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.000s 42.151us 5 5 100.00
edn_csr_aliasing 2.000s 21.033us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 4.000s 139.855us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 4.000s 139.855us 100 100 100.00
genbits 100 100 100.00
edn_genbits 4.000s 139.855us 100 100 100.00
interrupts 20 20 100.00
edn_intr 2.000s 20.663us 20 20 100.00
alerts 200 200 100.00
edn_alert 3.000s 53.773us 200 200 100.00
errs 100 100 100.00
edn_err 3.000s 46.329us 100 100 100.00
disable 90 100 90.00
edn_disable 2.000s 86.874us 50 50 100.00
edn_disable_auto_req_mode 12.000s 500.000us 40 50 80.00
stress_all 30 30 100.00
edn_stress_all 8.000s 513.929us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 2.000s 16.471us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 2.000s 23.067us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 6.000s 1405.717us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 6.000s 1405.717us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 2.000s 35.014us 1 1 100.00
edn_csr_rw 1.000s 42.151us 5 5 100.00
edn_csr_aliasing 2.000s 21.033us 1 1 100.00
edn_same_csr_outstanding 2.000s 16.247us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 2.000s 35.014us 1 1 100.00
edn_csr_rw 1.000s 42.151us 5 5 100.00
edn_csr_aliasing 2.000s 21.033us 1 1 100.00
edn_same_csr_outstanding 2.000s 16.247us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 7.000s 639.897us 5 5 100.00
edn_tl_intg_err 3.000s 96.784us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 2.000s 15.734us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 3.000s 53.773us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.000s 639.897us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.000s 639.897us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.000s 639.897us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.000s 639.897us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 3.000s 53.773us 200 200 100.00
edn_sec_cm 7.000s 639.897us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 3.000s 53.773us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.000s 96.784us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 28 30 93.33
edn_stress_all_with_rand_reset 100.000s 13385.340us 28 30 93.33

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 9 test runs
edn_disable_auto_req_mode 108873427109419562895486302267316417709158374795228682613741907346804011717220 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 107261557538948284918383162346628788334799892209080027371883971797419508558284 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 101490256337128297093729733443893814398386450008812017833243890914279584137317 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 28356257582264878789820353929629467336602999062211982779729426817168550572853 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 47866546324492564853523699743319195714240357905875232271079333852021884553505 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 69204126411128017851596133982116971456414855025501078156879835249702704670463 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 33629436282089794008772561602122218365727942593225514257880156624165984833231 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 81413531449005853461666040261747258052030139558796509617561811871013290588839 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 69720636771874584170236519831670857486741357688526468471735371827353422220631 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_csrng_agent_*/csrng_agent_cov.sv, Line: *):(Time: * PS + *) Sampled value (INV) for coverpoint (worklib.csrng_agent_pkg::csrng_agent_cov::m_device_cmd_cg@*_*.csrng_cmd_cp) is an illegal value. 1 test run
edn_stress_all_with_rand_reset 71746163725843026067147252935890331284263486989703166380216478225747985686959 232
UVM_INFO @ 2331948183 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Running run_tl_errors_vseq 3/884
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/edn_edn0-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, Line: 31):(Time: 2396939846 PS + 7) Sampled value (INV) for coverpoint (worklib.csrng_agent_pkg::csrng_agent_cov::m_device_cmd_cg@11280_2.csrng_cmd_cp) is an illegal value.
UVM_INFO @ 2403783816 ps: (cip_base_vseq.sv:793) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Running intr test iteration 1/3
UVM_INFO @ 2404638009 ps: (cip_base_vseq.sv:793) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Running intr test iteration 2/3
UVM_ERROR (cip_base_vseq.sv:1287) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 98669652870611510925101535166430785098821284656255350163529634975934764199120 199
UVM_INFO @ 2344756053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:431) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 107070701659226979215838607704318492582359981390008843393437520360155308269196 103
UVM_INFO @ 25671949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---