Simulation Results: edn/edn1

 
06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.41 %
  • code
  • 95.86 %
  • assert
  • 97.92 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.62 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
99.01%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.050s 18.108us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.130s 15.352us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.100s 18.347us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.360s 1353.756us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.200s 130.058us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.680s 163.510us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.100s 18.347us 5 5 100.00
edn_csr_aliasing 1.200s 130.058us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 2.980s 265.702us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 2.980s 265.702us 100 100 100.00
genbits 100 100 100.00
edn_genbits 2.980s 265.702us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.410s 20.564us 20 20 100.00
alerts 200 200 100.00
edn_alert 2.150s 425.160us 200 200 100.00
errs 100 100 100.00
edn_err 1.530s 28.719us 100 100 100.00
disable 94 100 94.00
edn_disable 1.200s 39.637us 50 50 100.00
edn_disable_auto_req_mode 6.470s 500.000us 44 50 88.00
stress_all 30 30 100.00
edn_stress_all 6.760s 357.068us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.190s 13.149us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.050s 319.984us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.450s 158.784us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.450s 158.784us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.130s 15.352us 1 1 100.00
edn_csr_rw 1.100s 18.347us 5 5 100.00
edn_csr_aliasing 1.200s 130.058us 1 1 100.00
edn_same_csr_outstanding 1.730s 38.797us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.130s 15.352us 1 1 100.00
edn_csr_rw 1.100s 18.347us 5 5 100.00
edn_csr_aliasing 1.200s 130.058us 1 1 100.00
edn_same_csr_outstanding 1.730s 38.797us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 5.020s 1280.771us 5 5 100.00
edn_tl_intg_err 5.950s 451.525us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.230s 52.052us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 2.150s 425.160us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.020s 1280.771us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.020s 1280.771us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 5.020s 1280.771us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 5.020s 1280.771us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 2.150s 425.160us 200 200 100.00
edn_sec_cm 5.020s 1280.771us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 2.150s 425.160us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 5.950s 451.525us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 27 30 90.00
edn_stress_all_with_rand_reset 122.560s 48488.410us 27 30 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
edn_disable_auto_req_mode 59645025619530302377344839930165118388961805341682924805936424704382086392120 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 71477768823949242742850831392824974990943937018323949006102671519462330632990 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 6806711830772782268735709171915402213048987627797067760972051437311947859451 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 32903805800731704104575030922988503999351932726404631957948281559024522246044 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 2 test runs
edn_stress_all_with_rand_reset 82095806570631563767010589802344290733661394180693167303502533387927116333341 144
UVM_INFO @ 12703482041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 75119396462302595644254012504858626180719910290761223882967016774589661492184 195
UVM_INFO @ 11379197114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 2 test runs
edn_disable_auto_req_mode 40014924942590786176201770787149096133793317702609161759218245343068421648771 88
UVM_INFO @ 13699199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 41920643837176014746239500898309632024225168400886545879891989770575818001231 88
UVM_INFO @ 249355573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 83605079504925158132852835949743059040442947443886674957115873415362919697720 146
UVM_INFO @ 236857107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---