Simulation Results: hmac

 
06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.98 %
  • code
  • 96.11 %
  • assert
  • 97.82 %
  • func
  • 100.00 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 20.000s 12733.495us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 48.010us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 2.000s 75.307us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 15.000s 603.985us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.000s 104.032us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 638.000s 143212.032us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 2.000s 75.307us 5 5 100.00
hmac_csr_aliasing 5.000s 104.032us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 90.000s 6379.427us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 129.000s 1935.888us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 308.000s 13774.544us 30 30 100.00
hmac_test_sha384_vectors 634.000s 57691.083us 75 75 100.00
hmac_test_sha512_vectors 624.000s 40630.262us 75 75 100.00
hmac_test_hmac256_vectors 24.000s 1633.238us 50 50 100.00
hmac_test_hmac384_vectors 29.000s 1540.421us 60 60 100.00
hmac_test_hmac512_vectors 34.000s 355.266us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 42.000s 2355.629us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 348.000s 24788.464us 10 10 100.00
error 10 10 100.00
hmac_error 171.000s 27734.807us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 118.000s 5488.460us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 20.000s 12733.495us 10 10 100.00
hmac_long_msg 90.000s 6379.427us 10 10 100.00
hmac_back_pressure 129.000s 1935.888us 25 25 100.00
hmac_datapath_stress 348.000s 24788.464us 10 10 100.00
hmac_burst_wr 42.000s 2355.629us 50 50 100.00
hmac_stress_all 928.000s 68068.533us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 20.000s 12733.495us 10 10 100.00
hmac_long_msg 90.000s 6379.427us 10 10 100.00
hmac_back_pressure 129.000s 1935.888us 25 25 100.00
hmac_datapath_stress 348.000s 24788.464us 10 10 100.00
hmac_wipe_secret 118.000s 5488.460us 10 10 100.00
hmac_test_sha256_vectors 308.000s 13774.544us 30 30 100.00
hmac_test_sha384_vectors 634.000s 57691.083us 75 75 100.00
hmac_test_sha512_vectors 624.000s 40630.262us 75 75 100.00
hmac_test_hmac256_vectors 24.000s 1633.238us 50 50 100.00
hmac_test_hmac384_vectors 29.000s 1540.421us 60 60 100.00
hmac_test_hmac512_vectors 34.000s 355.266us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 20.000s 12733.495us 10 10 100.00
hmac_long_msg 90.000s 6379.427us 10 10 100.00
hmac_back_pressure 129.000s 1935.888us 25 25 100.00
hmac_datapath_stress 348.000s 24788.464us 10 10 100.00
hmac_burst_wr 42.000s 2355.629us 50 50 100.00
hmac_error 171.000s 27734.807us 10 10 100.00
hmac_wipe_secret 118.000s 5488.460us 10 10 100.00
hmac_test_sha256_vectors 308.000s 13774.544us 30 30 100.00
hmac_test_sha384_vectors 634.000s 57691.083us 75 75 100.00
hmac_test_sha512_vectors 624.000s 40630.262us 75 75 100.00
hmac_test_hmac256_vectors 24.000s 1633.238us 50 50 100.00
hmac_test_hmac384_vectors 29.000s 1540.421us 60 60 100.00
hmac_test_hmac512_vectors 34.000s 355.266us 75 75 100.00
hmac_stress_all 928.000s 68068.533us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 928.000s 68068.533us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 2.000s 12.650us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 2.000s 73.986us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 6.000s 325.774us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 6.000s 325.774us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 2.000s 48.010us 1 1 100.00
hmac_csr_rw 2.000s 75.307us 5 5 100.00
hmac_csr_aliasing 5.000s 104.032us 1 1 100.00
hmac_same_csr_outstanding 3.000s 143.546us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 2.000s 48.010us 1 1 100.00
hmac_csr_rw 2.000s 75.307us 5 5 100.00
hmac_csr_aliasing 5.000s 104.032us 1 1 100.00
hmac_same_csr_outstanding 3.000s 143.546us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 2.000s 99.556us 5 5 100.00
hmac_tl_intg_err 6.000s 550.144us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 6.000s 550.144us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 20.000s 12733.495us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 8.000s 224.125us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 258.000s 10249.403us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 4.000s 174.823us 1 1 100.00