Simulation Results: keymgr_dpe

 
06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 66.43 %
  • code
  • 84.10 %
  • assert
  • 97.14 %
  • func
  • 18.04 %
  • block
  • 98.09 %
  • line
  • 98.74 %
  • branch
  • 93.62 %
  • toggle
  • 62.50 %
  • FSM
  • 81.54 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.57%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
keymgr_dpe_smoke 35.000s 6388.580us 10 10 100.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 2.000s 31.553us 1 1 100.00
csr_rw 5 5 100.00
keymgr_dpe_csr_rw 3.000s 86.486us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 7.000s 2205.079us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 2.000s 46.289us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 2.000s 52.597us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_dpe_csr_rw 3.000s 86.486us 5 5 100.00
keymgr_dpe_csr_aliasing 2.000s 46.289us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 10 10 100.00
keymgr_dpe_intr_test 2.000s 73.469us 10 10 100.00
alert_test 10 10 100.00
keymgr_dpe_alert_test 2.000s 85.837us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_dpe_tl_errors 6.000s 133.339us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_dpe_tl_errors 6.000s 133.339us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_dpe_csr_hw_reset 2.000s 31.553us 1 1 100.00
keymgr_dpe_csr_rw 3.000s 86.486us 5 5 100.00
keymgr_dpe_csr_aliasing 2.000s 46.289us 1 1 100.00
keymgr_dpe_same_csr_outstanding 3.000s 77.928us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_dpe_csr_hw_reset 2.000s 31.553us 1 1 100.00
keymgr_dpe_csr_rw 3.000s 86.486us 5 5 100.00
keymgr_dpe_csr_aliasing 2.000s 46.289us 1 1 100.00
keymgr_dpe_same_csr_outstanding 3.000s 77.928us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
keymgr_dpe_sec_cm 15.000s 1114.322us 5 5 100.00
keymgr_dpe_tl_intg_err 7.000s 832.414us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.000s 130.403us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.000s 130.403us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.000s 130.403us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.000s 130.403us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 8.000s 939.616us 19 20 95.00
prim_count_check 5 5 100.00
keymgr_dpe_sec_cm 15.000s 1114.322us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_dpe_sec_cm 15.000s 1114.322us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1381) [keymgr_dpe_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! 1 test run
keymgr_dpe_shadow_reg_errors_with_csr_rw 77730533193299746788228040848272908938335518129637794594870790262332924525800 85
UVM_INFO @ 27374054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---