Simulation Results: kmac/masked

 
06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.03 %
  • code
  • 94.26 %
  • assert
  • 98.85 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.10 %
  • cond
  • 94.78 %
  • toggle
  • 99.89 %
  • FSM
  • 80.28 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
kmac_smoke 72.770s 20619.321us 20 20 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.130s 105.474us 1 1 100.00
csr_rw 5 5 100.00
kmac_csr_rw 1.270s 64.125us 5 5 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 8.130s 3483.759us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.680s 263.560us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
kmac_csr_mem_rw_with_rand_reset 2.740s 298.032us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
kmac_csr_rw 1.270s 64.125us 5 5 100.00
kmac_csr_aliasing 5.680s 263.560us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.860s 14.537us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.160s 18.228us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 20 20 100.00
kmac_long_msg_and_output 4522.240s 133593.548us 20 20 100.00
burst_write 20 20 100.00
kmac_burst_write 1224.660s 229090.323us 20 20 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1799.180s 120634.505us 5 5 100.00
kmac_test_vectors_sha3_256 2872.230s 716814.965us 5 5 100.00
kmac_test_vectors_sha3_384 1872.210s 593230.209us 5 5 100.00
kmac_test_vectors_sha3_512 1374.150s 70947.616us 5 5 100.00
kmac_test_vectors_shake_128 2137.270s 43504.871us 5 5 100.00
kmac_test_vectors_shake_256 496.990s 297452.002us 5 5 100.00
kmac_test_vectors_kmac 3.230s 265.236us 5 5 100.00
kmac_test_vectors_kmac_xof 3.120s 112.401us 5 5 100.00
sideload 20 20 100.00
kmac_sideload 421.950s 43378.678us 20 20 100.00
app 25 25 100.00
kmac_app 427.950s 300931.427us 25 25 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 335.510s 20981.970us 10 10 100.00
entropy_refresh 20 20 100.00
kmac_entropy_refresh 365.990s 21089.620us 20 20 100.00
error 20 20 100.00
kmac_error 445.980s 46422.141us 20 20 100.00
key_error 20 20 100.00
kmac_key_error 17.160s 33064.024us 20 20 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 8.760s 1336.725us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 42.540s 12034.137us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 28.960s 6601.886us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 63.250s 8090.923us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 42.480s 2064.743us 50 50 100.00
stress_all 20 20 100.00
kmac_stress_all 3271.010s 472131.107us 20 20 100.00
intr_test 10 10 100.00
kmac_intr_test 1.100s 253.493us 10 10 100.00
alert_test 10 10 100.00
kmac_alert_test 1.050s 41.163us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
kmac_tl_errors 4.220s 1287.715us 25 25 100.00
tl_d_illegal_access 25 25 100.00
kmac_tl_errors 4.220s 1287.715us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
kmac_csr_hw_reset 1.130s 105.474us 1 1 100.00
kmac_csr_rw 1.270s 64.125us 5 5 100.00
kmac_csr_aliasing 5.680s 263.560us 1 1 100.00
kmac_same_csr_outstanding 2.220s 105.120us 5 5 100.00
tl_d_partial_access 12 12 100.00
kmac_csr_hw_reset 1.130s 105.474us 1 1 100.00
kmac_csr_rw 1.270s 64.125us 5 5 100.00
kmac_csr_aliasing 5.680s 263.560us 1 1 100.00
kmac_same_csr_outstanding 2.220s 105.120us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.580s 206.396us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.580s 206.396us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.580s 206.396us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.580s 206.396us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 5.430s 3325.150us 20 20 100.00
tl_intg_err 30 30 100.00
kmac_sec_cm 87.640s 8000.616us 5 5 100.00
kmac_tl_intg_err 5.670s 246.431us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
kmac_tl_intg_err 5.670s 246.431us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 42.480s 2064.743us 50 50 100.00
sec_cm_sw_key_key_masking 20 20 100.00
kmac_smoke 72.770s 20619.321us 20 20 100.00
sec_cm_key_sideload 20 20 100.00
kmac_sideload 421.950s 43378.678us 20 20 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.580s 206.396us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 87.640s 8000.616us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 87.640s 8000.616us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 87.640s 8000.616us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 20 20 100.00
kmac_smoke 72.770s 20619.321us 20 20 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 42.480s 2064.743us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 87.640s 8000.616us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 319.820s 66714.790us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 20 20 100.00
kmac_smoke 72.770s 20619.321us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 245.320s 21222.428us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:858) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 2 test runs
kmac_stress_all_with_rand_reset 54473979079490270720493013686595731217500446978762328038968086709493490114389 198
UVM_INFO @ 1122810359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 41569063944023964689699849499968623844474163592681266366997494404115308010169 223
UVM_INFO @ 1649016331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---