Simulation Results: kmac/unmasked

 
06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.56 %
  • code
  • 92.39 %
  • assert
  • 97.90 %
  • func
  • 96.39 %
  • line
  • 97.66 %
  • branch
  • 95.95 %
  • cond
  • 94.77 %
  • toggle
  • 100.00 %
  • FSM
  • 73.55 %
Validation stages
V1
100.00%
V2
95.73%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
kmac_smoke 62.930s 3908.721us 20 20 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.370s 115.910us 1 1 100.00
csr_rw 5 5 100.00
kmac_csr_rw 1.520s 100.086us 5 5 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 6.710s 156.088us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.530s 1513.025us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
kmac_csr_mem_rw_with_rand_reset 2.420s 37.541us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
kmac_csr_rw 1.520s 100.086us 5 5 100.00
kmac_csr_aliasing 5.530s 1513.025us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 1.020s 22.647us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.440s 96.939us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 20 20 100.00
kmac_long_msg_and_output 4373.010s 136734.401us 20 20 100.00
burst_write 20 20 100.00
kmac_burst_write 925.600s 38541.503us 20 20 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2615.600s 504489.594us 5 5 100.00
kmac_test_vectors_sha3_256 48.870s 6024.435us 5 5 100.00
kmac_test_vectors_sha3_384 1567.530s 247271.179us 5 5 100.00
kmac_test_vectors_sha3_512 1174.950s 335460.787us 5 5 100.00
kmac_test_vectors_shake_128 1685.260s 42883.932us 5 5 100.00
kmac_test_vectors_shake_256 319.950s 91888.267us 5 5 100.00
kmac_test_vectors_kmac 2.620s 239.201us 5 5 100.00
kmac_test_vectors_kmac_xof 2.910s 489.214us 5 5 100.00
sideload 20 20 100.00
kmac_sideload 404.190s 24576.886us 20 20 100.00
app 25 25 100.00
kmac_app 289.430s 20200.542us 25 25 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 368.390s 352551.957us 10 10 100.00
entropy_refresh 20 20 100.00
kmac_entropy_refresh 358.890s 44735.553us 20 20 100.00
error 20 20 100.00
kmac_error 402.410s 23205.834us 20 20 100.00
key_error 20 20 100.00
kmac_key_error 12.240s 1890.911us 20 20 100.00
sideload_invalid 32 50 64.00
kmac_sideload_invalid 110.460s 10023.112us 32 50 64.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 33.960s 1978.683us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 40.160s 5718.714us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 55.510s 25863.163us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 22.550s 629.192us 50 50 100.00
stress_all 20 20 100.00
kmac_stress_all 2783.460s 113532.216us 20 20 100.00
intr_test 10 10 100.00
kmac_intr_test 1.160s 23.301us 10 10 100.00
alert_test 10 10 100.00
kmac_alert_test 1.200s 60.389us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
kmac_tl_errors 4.680s 1461.744us 25 25 100.00
tl_d_illegal_access 25 25 100.00
kmac_tl_errors 4.680s 1461.744us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
kmac_csr_hw_reset 1.370s 115.910us 1 1 100.00
kmac_csr_rw 1.520s 100.086us 5 5 100.00
kmac_csr_aliasing 5.530s 1513.025us 1 1 100.00
kmac_same_csr_outstanding 2.410s 162.707us 5 5 100.00
tl_d_partial_access 12 12 100.00
kmac_csr_hw_reset 1.370s 115.910us 1 1 100.00
kmac_csr_rw 1.520s 100.086us 5 5 100.00
kmac_csr_aliasing 5.530s 1513.025us 1 1 100.00
kmac_same_csr_outstanding 2.410s 162.707us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.500s 83.768us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.500s 83.768us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.500s 83.768us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.500s 83.768us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 5.930s 977.958us 20 20 100.00
tl_intg_err 30 30 100.00
kmac_sec_cm 74.820s 10149.465us 5 5 100.00
kmac_tl_intg_err 5.400s 459.724us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
kmac_tl_intg_err 5.400s 459.724us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 22.550s 629.192us 50 50 100.00
sec_cm_sw_key_key_masking 20 20 100.00
kmac_smoke 62.930s 3908.721us 20 20 100.00
sec_cm_key_sideload 20 20 100.00
kmac_sideload 404.190s 24576.886us 20 20 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.500s 83.768us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 74.820s 10149.465us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 74.820s 10149.465us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 74.820s 10149.465us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 20 20 100.00
kmac_smoke 62.930s 3908.721us 20 20 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 22.550s 629.192us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 74.820s 10149.465us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 338.550s 19745.493us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 20 20 100.00
kmac_smoke 62.930s 3908.721us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
kmac_stress_all_with_rand_reset 239.210s 10430.823us 7 10 70.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 8 test runs
kmac_sideload_invalid 82756653130641773110690184312804572214541456567644642545697059283147302008720 78
UVM_INFO @ 10039984278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 25486471651076281614157525392693613179809647805010268233695994172268669525199 78
UVM_INFO @ 10166918454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 34617559327616056942823742050679632792774887899989959637907627347342913429106 78
UVM_INFO @ 10010956430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 78217138517477740504241847243420099568633488239244904496028528245100919605834 78
UVM_INFO @ 10023029074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 81938213287478069475152830231497867641255980996849268786965965598313066472689 78
UVM_INFO @ 10018936621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 106059139636153552293336401551712770819237730616527825491482069038761528019089 78
UVM_INFO @ 10018411322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 85038908484969800292923202196107173488521399035903871383537755264420023956172 78
UVM_INFO @ 10017363644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 1985806774039590615127045706742875492087088537656968789027464683603885754633 78
UVM_INFO @ 10012363154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
kmac_stress_all_with_rand_reset 83566558334580686385386748020131027138738629242913925754856694410981469325880 108
UVM_INFO @ 7422394905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 87609064114519577633441072297673798118075677535653256662180186342672786202725 126
UVM_INFO @ 8169578582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 43253484049755762296803274215947863007715142660130621173892984706547432170485 135
UVM_INFO @ 4532341097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) 2 test runs
kmac_sideload_invalid 5286849592834861207422126095152284552880529964741123866323827648860823357810 84
UVM_INFO @ 10043761949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 111843949061153974932856711219886643299086076550529537121327367661488530085443 83
UVM_INFO @ 10163176177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) 2 test runs
kmac_sideload_invalid 64219304087559969904071274053744257409137453239594196312247113481265423735288 80
UVM_INFO @ 10268283539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 93745634938698034705263629021026508326293718844141205028773649305985434314315 80
UVM_INFO @ 10141466048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) 2 test runs
kmac_sideload_invalid 85101466366715050807706186858879477026593648044237852869607402757774622807959 79
UVM_INFO @ 10023112157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 77420890510807646408805796241868235937836582070038461211829490770372338271644 79
UVM_INFO @ 10026772563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) 1 test run
kmac_sideload_invalid 103885158222553414073761891340463850360720256351594502648049900698909072565690 94
UVM_INFO @ 10130082857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) 1 test run
kmac_sideload_invalid 42015039620739071218157199995553054530556414766563462795826807757151923349879 87
UVM_INFO @ 10242656026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) 1 test run
kmac_sideload_invalid 106417423180490920516302158579400427778134663791294530461093064680463512581613 85
UVM_INFO @ 10123033632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) 1 test run
kmac_sideload_invalid 72093417540635046528673609551701607549610794795463558342101455991099868528706 81
UVM_INFO @ 10267742146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---