Simulation Results: lc_ctrl/volatile_unlock_disabled

 
06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.51 %
  • code
  • 93.58 %
  • assert
  • 96.83 %
  • func
  • 90.13 %
  • block
  • 96.75 %
  • line
  • 97.38 %
  • branch
  • 91.72 %
  • toggle
  • 89.97 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.53%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 5.000s 291.119us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 16.000s 26.720us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 2.000s 14.700us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 18.000s 38.777us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 22.000s 21.622us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 7.000s 164.252us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 2.000s 14.700us 5 5 100.00
lc_ctrl_csr_aliasing 22.000s 21.622us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 5.000s 104.165us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 13.000s 299.506us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 23.000s 23.692us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.000s 469.224us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 10.000s 1472.585us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 16.000s 1638.133us 20 20 100.00
security_escalation 138 140 98.57
lc_ctrl_state_failure 10.000s 1472.585us 20 20 100.00
lc_ctrl_prog_failure 4.000s 469.224us 20 20 100.00
lc_ctrl_errors 16.000s 1638.133us 20 20 100.00
lc_ctrl_security_escalation 11.000s 434.792us 20 20 100.00
lc_ctrl_jtag_state_failure 84.000s 10143.537us 19 20 95.00
lc_ctrl_jtag_prog_failure 19.000s 822.694us 19 20 95.00
lc_ctrl_jtag_errors 51.000s 12870.724us 20 20 100.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 9.000s 389.081us 20 20 100.00
lc_ctrl_jtag_state_post_trans 21.000s 3795.442us 20 20 100.00
lc_ctrl_jtag_prog_failure 19.000s 822.694us 19 20 95.00
lc_ctrl_jtag_errors 51.000s 12870.724us 20 20 100.00
lc_ctrl_jtag_access 23.000s 5274.847us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 24.000s 993.546us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 782.926us 10 10 100.00
lc_ctrl_jtag_csr_rw 4.000s 384.124us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 36.000s 1951.205us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 21.000s 2026.677us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 8.000s 183.406us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.000s 130.191us 10 10 100.00
lc_ctrl_jtag_alert_test 4.000s 461.881us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 29.000s 3065.881us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 15.988us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 199.000s 82284.273us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 24.000s 97.745us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 6.000s 786.971us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 6.000s 786.971us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 16.000s 26.720us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.700us 5 5 100.00
lc_ctrl_csr_aliasing 22.000s 21.622us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 32.930us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 16.000s 26.720us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.700us 5 5 100.00
lc_ctrl_csr_aliasing 22.000s 21.622us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 32.930us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 5.000s 894.971us 5 5 100.00
lc_ctrl_tl_intg_err 5.000s 135.322us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 5.000s 135.322us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 13.000s 299.506us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 1472.585us 20 20 100.00
lc_ctrl_sec_cm 5.000s 894.971us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 1472.585us 20 20 100.00
lc_ctrl_sec_cm 5.000s 894.971us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.000s 1472.585us 20 20 100.00
lc_ctrl_sec_cm 5.000s 894.971us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.000s 1472.585us 20 20 100.00
lc_ctrl_sec_cm 5.000s 894.971us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 1472.585us 20 20 100.00
lc_ctrl_sec_cm 5.000s 894.971us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 1472.585us 20 20 100.00
lc_ctrl_sec_cm 5.000s 894.971us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 1472.585us 20 20 100.00
lc_ctrl_sec_cm 5.000s 894.971us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 10.000s 1472.585us 20 20 100.00
lc_ctrl_sec_cm 5.000s 894.971us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 11.000s 434.792us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 5.000s 104.165us 20 20 100.00
lc_ctrl_jtag_state_post_trans 21.000s 3795.442us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.000s 810.738us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.000s 810.738us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 10.000s 1351.798us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.000s 695.797us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.000s 695.797us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 58.000s 19373.377us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
lc_ctrl_stress_all_with_rand_reset 96733237847188454033399284876920578753184238096304289421104880474927335265610 176
UVM_INFO @ 1064093715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108991849011164268681135650627236386694927690977879311588877166302995345023257 182
UVM_INFO @ 2264012248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 114107849669622872018089622260421984918464471055699750602001244671272757207293 1504
UVM_INFO @ 4704361347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108248910015930565247798734745707649807803726690079439667730925056623717064765 617
UVM_INFO @ 1388583352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 101708242219123365753468959269520720931269440088996024917467014447651667844379 165
UVM_INFO @ 4078145401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 83351856083832178196935360188211043687106783609632474326008675460138485583893 3159
UVM_INFO @ 19373377070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 1 test run
lc_ctrl_jtag_prog_failure 34828460391894883948847783541712645982321882443063589922979010156555183213301 177
UVM_INFO @ 460543133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_failure 112520303664918296507416184934827785156242761898867818458739810447061369094456 179
UVM_INFO @ 142536654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---