Simulation Results: lc_ctrl/volatile_unlock_enabled

 
06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.52 %
  • code
  • 94.52 %
  • assert
  • 96.54 %
  • func
  • 89.49 %
  • block
  • 97.16 %
  • line
  • 97.69 %
  • branch
  • 92.79 %
  • toggle
  • 89.99 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
99.30%
V2S
100.00%
V3
30.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 5.000s 186.078us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 22.834us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 2.000s 148.059us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 363.195us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 22.610us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 19.130us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 2.000s 148.059us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 22.610us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 4.000s 89.255us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 14.000s 327.981us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 2.000s 21.640us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 5.000s 563.604us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 10.000s 388.932us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 11.000s 6245.632us 19 20 95.00
security_escalation 137 140 97.86
lc_ctrl_state_failure 10.000s 388.932us 20 20 100.00
lc_ctrl_prog_failure 5.000s 563.604us 20 20 100.00
lc_ctrl_errors 11.000s 6245.632us 19 20 95.00
lc_ctrl_security_escalation 11.000s 2256.252us 20 20 100.00
lc_ctrl_jtag_state_failure 77.000s 74610.653us 18 20 90.00
lc_ctrl_jtag_prog_failure 13.000s 771.628us 20 20 100.00
lc_ctrl_jtag_errors 87.000s 10028.184us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 9.000s 6167.632us 20 20 100.00
lc_ctrl_jtag_state_post_trans 18.000s 1913.809us 20 20 100.00
lc_ctrl_jtag_prog_failure 13.000s 771.628us 20 20 100.00
lc_ctrl_jtag_errors 87.000s 10028.184us 20 20 100.00
lc_ctrl_jtag_access 19.000s 926.329us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 29.000s 18317.325us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 103.825us 10 10 100.00
lc_ctrl_jtag_csr_rw 4.000s 193.483us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 12.000s 10292.292us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 12.000s 553.187us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 49.186us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 97.514us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 37.608us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 10.000s 329.509us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 98.696us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 117.000s 6809.554us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 3.000s 30.043us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 139.880us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 139.880us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 22.834us 1 1 100.00
lc_ctrl_csr_rw 2.000s 148.059us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 22.610us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 519.013us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 22.834us 1 1 100.00
lc_ctrl_csr_rw 2.000s 148.059us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 22.610us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 519.013us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 5.000s 1072.953us 5 5 100.00
lc_ctrl_tl_intg_err 4.000s 540.898us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.000s 540.898us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 14.000s 327.981us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 388.932us 20 20 100.00
lc_ctrl_sec_cm 5.000s 1072.953us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 388.932us 20 20 100.00
lc_ctrl_sec_cm 5.000s 1072.953us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.000s 388.932us 20 20 100.00
lc_ctrl_sec_cm 5.000s 1072.953us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.000s 388.932us 20 20 100.00
lc_ctrl_sec_cm 5.000s 1072.953us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 388.932us 20 20 100.00
lc_ctrl_sec_cm 5.000s 1072.953us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 388.932us 20 20 100.00
lc_ctrl_sec_cm 5.000s 1072.953us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 388.932us 20 20 100.00
lc_ctrl_sec_cm 5.000s 1072.953us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 10.000s 388.932us 20 20 100.00
lc_ctrl_sec_cm 5.000s 1072.953us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 11.000s 2256.252us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 4.000s 89.255us 20 20 100.00
lc_ctrl_jtag_state_post_trans 18.000s 1913.809us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 12.000s 2559.513us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 12.000s 2559.513us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 12.000s 3380.846us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.000s 1419.401us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.000s 1419.401us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
lc_ctrl_stress_all_with_rand_reset 74.000s 14760.370us 3 10 30.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
lc_ctrl_stress_all_with_rand_reset 22370401940774912948304970193927057575502046971967186130160307264759840496584 161
UVM_INFO @ 215204877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 59907914748860132010855261882535075647674573198085653317003343928166954769288 954
UVM_INFO @ 6362812415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 16240523385079756153450700908588338712868916800671165549876978919908969911514 895
UVM_INFO @ 14189344503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 61972949962154827410956699050163392956306070856186931950225614038877302059201 692
UVM_INFO @ 32908031033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 57052729013179043265365529226216701703420788081989839095566189718153694446656 3238
UVM_INFO @ 2382606471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 2 test runs
lc_ctrl_stress_all_with_rand_reset 42311500116142389047355354269119555336278328818442906790959015817485486559830 382
UVM_INFO @ 712797877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 69357869386689471556416657692907961911524304259020295307970918933485411174094 697
UVM_INFO @ 2596816580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_state_failure 28781108350517781049645361230338046238285972811638166440222935762771752122670 178
UVM_INFO @ 483267795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 42120166989006904190913667347678240733883552342989325038670157366242647858640 177
UVM_INFO @ 203389184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_errors 107348471468916474477090744485943983729024348226154833142752593094035331915750 268
UVM_INFO @ 27681616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---