Simulation Results: otbn

 
06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.56 %
  • code
  • 95.53 %
  • assert
  • 91.17 %
  • func
  • 100.00 %
  • block
  • 99.44 %
  • line
  • 99.59 %
  • branch
  • 92.88 %
  • toggle
  • 89.63 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.16%
V2S
97.26%
V3
60.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 234.115us 1 1 100.00
single_binary 100 100 100.00
otbn_single 157.000s 751.599us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 9.000s 21.683us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 9.000s 43.011us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 14.000s 522.634us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 9.000s 41.253us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 12.000s 247.216us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 9.000s 43.011us 5 5 100.00
otbn_csr_aliasing 9.000s 41.253us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 65.000s 10187.075us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 65.000s 10096.934us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 80.000s 348.828us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 68.000s 363.814us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 90.000s 516.708us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 269.000s 541.444us 10 10 100.00
lc_escalation 57 60 95.00
otbn_escalate 33.000s 125.442us 57 60 95.00
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 7.000s 28.575us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 24.000s 745.015us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 10.000s 55.548us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 8.000s 24.721us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 7.000s 545.070us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 7.000s 545.070us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 9.000s 21.683us 1 1 100.00
otbn_csr_rw 9.000s 43.011us 5 5 100.00
otbn_csr_aliasing 9.000s 41.253us 1 1 100.00
otbn_same_csr_outstanding 5.000s 16.615us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 9.000s 21.683us 1 1 100.00
otbn_csr_rw 9.000s 43.011us 5 5 100.00
otbn_csr_aliasing 9.000s 41.253us 1 1 100.00
otbn_same_csr_outstanding 5.000s 16.615us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 12.000s 29.340us 10 10 100.00
otbn_dmem_err 22.000s 77.346us 15 15 100.00
internal_integrity 13 17 76.47
otbn_alu_bignum_mod_err 104.000s 436.191us 5 5 100.00
otbn_controller_ispr_rdata_err 9.000s 210.510us 2 5 40.00
otbn_mac_bignum_acc_err 9.000s 66.972us 4 5 80.00
otbn_urnd_err 6.000s 10.565us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 7.000s 25.644us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 7.000s 41.196us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 9.000s 460.247us 9 10 90.00
tl_intg_err 29 30 96.67
otbn_sec_cm 193.000s 1782.916us 4 5 80.00
otbn_tl_intg_err 35.000s 183.878us 25 25 100.00
passthru_mem_tl_intg_err 5 5 100.00
otbn_passthru_mem_tl_intg_err 76.000s 220.754us 5 5 100.00
prim_fsm_check 4 5 80.00
otbn_sec_cm 193.000s 1782.916us 4 5 80.00
prim_count_check 4 5 80.00
otbn_sec_cm 193.000s 1782.916us 4 5 80.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 234.115us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 22.000s 77.346us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 12.000s 29.340us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 35.000s 183.878us 25 25 100.00
sec_cm_controller_fsm_global_esc 57 60 95.00
otbn_escalate 33.000s 125.442us 57 60 95.00
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 12.000s 29.340us 10 10 100.00
otbn_dmem_err 22.000s 77.346us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 28.575us 5 5 100.00
otbn_illegal_mem_acc 7.000s 25.644us 5 5 100.00
otbn_sec_cm 193.000s 1782.916us 4 5 80.00
sec_cm_controller_fsm_sparse 4 5 80.00
otbn_sec_cm 193.000s 1782.916us 4 5 80.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 157.000s 751.599us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 12.000s 29.340us 10 10 100.00
otbn_dmem_err 22.000s 77.346us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 28.575us 5 5 100.00
otbn_illegal_mem_acc 7.000s 25.644us 5 5 100.00
otbn_sec_cm 193.000s 1782.916us 4 5 80.00
sec_cm_scramble_ctrl_fsm_sparse 4 5 80.00
otbn_sec_cm 193.000s 1782.916us 4 5 80.00
sec_cm_start_stop_ctrl_fsm_global_esc 57 60 95.00
otbn_escalate 33.000s 125.442us 57 60 95.00
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 12.000s 29.340us 10 10 100.00
otbn_dmem_err 22.000s 77.346us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 28.575us 5 5 100.00
otbn_illegal_mem_acc 7.000s 25.644us 5 5 100.00
otbn_sec_cm 193.000s 1782.916us 4 5 80.00
sec_cm_start_stop_ctrl_fsm_sparse 4 5 80.00
otbn_sec_cm 193.000s 1782.916us 4 5 80.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 157.000s 751.599us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 10.000s 45.331us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 9.000s 22.017us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 47.000s 167.777us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 47.000s 167.777us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 41.000s 521.307us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 4 5 80.00
otbn_sec_cm 193.000s 1782.916us 4 5 80.00
sec_cm_stack_wr_ptr_ctr_redun 4 5 80.00
otbn_sec_cm 193.000s 1782.916us 4 5 80.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 13.000s 62.248us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 4 5 80.00
otbn_sec_cm 193.000s 1782.916us 4 5 80.00
sec_cm_loop_stack_ctr_redun 4 5 80.00
otbn_sec_cm 193.000s 1782.916us 4 5 80.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 14.000s 73.435us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 14.000s 73.435us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 13.000s 335.548us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 157.000s 751.599us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 157.000s 751.599us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 157.000s 751.599us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 90.000s 516.708us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 157.000s 751.599us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 157.000s 751.599us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 15.000s 41.677us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 157.000s 751.599us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 4 5 80.00
otbn_sec_cm 193.000s 1782.916us 4 5 80.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
otbn_stress_all_with_rand_reset 447.000s 6276.904us 6 10 60.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 22.563us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 4 test runs
otbn_controller_ispr_rdata_err 7007494976553089724832897257585598129001407662587243617301271034938753660780 159
UVM_INFO @ 93763651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_mac_bignum_acc_err 82200829600695472811278885393928045626524241810208868768855309919578810885355 176
UVM_INFO @ 66972455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_controller_ispr_rdata_err 5242994297246163256802247120605318431346408839244307953649572340622469896524 110
UVM_INFO @ 62493455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_controller_ispr_rdata_err 72181474063513876871609362718391663679668100370539859249524113292084324651804 107
UVM_INFO @ 30678535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 2 test runs
otbn_stress_all_with_rand_reset 90999831706723368494339249255082888665514506604285256442718170022451425309330 296
UVM_INFO @ 4796559211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 8061178008422940547788522956222260402883104611464895103982864120109076020058 462
UVM_INFO @ 1036360712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
otbn_stress_all_with_rand_reset 3797861250730555048713711134188872436168921342606863283256055172538608943817 374
UVM_INFO @ 841693704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 109153485066962022068132872770069890870062642211563728025901905818071413647551 665
UVM_INFO @ 6276903563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:507) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. 2 test runs
otbn_escalate 18536555682096642430868299727734775747749123090250215506271580432250267876063 107
UVM_INFO @ 56366031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 83498611703052760819061550802810537022451388573669984472229140290925925481398 110
UVM_INFO @ 43980185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn_rnd.sv,233): Assertion UrndNoReseedOnReset_A has failed 1 test run
otbn_sec_cm 106846265235297090530229496003523841734979770860501937856706621233490351916582 130
UVM_ERROR @ 159133111 ps: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 159133111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_partial_wipe 15625603712669543759054482528391594641900435039438751394268866353889385032956 106
UVM_ERROR @ 6941498 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 6941498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_escalate 57330881455826542433891635358378226361170856303162318393808707391867234407073 108
UVM_INFO @ 1480324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---