Simulation Results: otp_ctrl

 
06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.54 %
  • code
  • 80.97 %
  • assert
  • 94.60 %
  • func
  • 81.05 %
  • line
  • 88.38 %
  • branch
  • 86.56 %
  • cond
  • 88.52 %
  • toggle
  • 88.85 %
  • FSM
  • 52.56 %
Validation stages
V1
84.62%
V2
72.64%
V2S
73.94%
V3
4.95%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.670s 858.785us 1 1 100.00
smoke 7 10 70.00
otp_ctrl_smoke 12.970s 650.023us 7 10 70.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 4.100s 1719.106us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 2.740s 56.469us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 6.610s 553.180us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 7.970s 547.880us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.270s 481.796us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 2.740s 56.469us 5 5 100.00
otp_ctrl_csr_aliasing 7.970s 547.880us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.760s 43.229us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.960s 57.012us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 186.760s 105540.085us 0 1 0.00
init_fail 215 300 71.67
otp_ctrl_init_fail 8.520s 3579.279us 215 300 71.67
partition_check 26 60 43.33
otp_ctrl_background_chks 19.100s 2257.720us 4 10 40.00
otp_ctrl_check_fail 35.310s 3036.605us 22 50 44.00
regwen_during_otp_init 18 30 60.00
otp_ctrl_regwen 15.360s 3765.739us 18 30 60.00
partition_lock 12 30 40.00
otp_ctrl_dai_lock 37.750s 5341.677us 12 30 40.00
interface_key_check 4 10 40.00
otp_ctrl_parallel_key_req 18.870s 7498.087us 4 10 40.00
lc_interactions 185 210 88.10
otp_ctrl_parallel_lc_req 21.770s 1645.066us 4 10 40.00
otp_ctrl_parallel_lc_esc 58.380s 26902.262us 181 200 90.50
otp_dai_errors 22 25 88.00
otp_ctrl_dai_errs 93.500s 42478.406us 22 25 88.00
otp_macro_errors 3 10 30.00
otp_ctrl_macro_errs 27.120s 4663.594us 3 10 30.00
test_access 4 10 40.00
otp_ctrl_test_access 32.670s 14735.519us 4 10 40.00
stress_all 1 10 10.00
otp_ctrl_stress_all 95.770s 22188.012us 1 10 10.00
intr_test 10 10 100.00
otp_ctrl_intr_test 2.500s 57.201us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 2.920s 180.505us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 8.860s 3149.264us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 8.860s 3149.264us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 4.100s 1719.106us 1 1 100.00
otp_ctrl_csr_rw 2.740s 56.469us 5 5 100.00
otp_ctrl_csr_aliasing 7.970s 547.880us 1 1 100.00
otp_ctrl_same_csr_outstanding 5.790s 2222.853us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 4.100s 1719.106us 1 1 100.00
otp_ctrl_csr_rw 2.740s 56.469us 5 5 100.00
otp_ctrl_csr_aliasing 7.970s 547.880us 1 1 100.00
otp_ctrl_same_csr_outstanding 5.790s 2222.853us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
tl_intg_err 30 30 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
otp_ctrl_tl_intg_err 56.260s 23646.532us 25 25 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
otp_ctrl_tl_intg_err 56.260s 23646.532us 25 25 100.00
sec_cm_secret_mem_scramble 7 10 70.00
otp_ctrl_smoke 12.970s 650.023us 7 10 70.00
sec_cm_part_mem_digest 7 10 70.00
otp_ctrl_smoke 12.970s 650.023us 7 10 70.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_dai_fsm_local_esc 186 205 90.73
otp_ctrl_parallel_lc_esc 58.380s 26902.262us 181 200 90.50
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_lci_fsm_local_esc 181 200 90.50
otp_ctrl_parallel_lc_esc 58.380s 26902.262us 181 200 90.50
sec_cm_kdi_fsm_local_esc 181 200 90.50
otp_ctrl_parallel_lc_esc 58.380s 26902.262us 181 200 90.50
sec_cm_part_fsm_local_esc 184 210 87.62
otp_ctrl_parallel_lc_esc 58.380s 26902.262us 181 200 90.50
otp_ctrl_macro_errs 27.120s 4663.594us 3 10 30.00
sec_cm_scrmbl_fsm_local_esc 181 200 90.50
otp_ctrl_parallel_lc_esc 58.380s 26902.262us 181 200 90.50
sec_cm_timer_fsm_local_esc 186 205 90.73
otp_ctrl_parallel_lc_esc 58.380s 26902.262us 181 200 90.50
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_dai_fsm_global_esc 186 205 90.73
otp_ctrl_parallel_lc_esc 58.380s 26902.262us 181 200 90.50
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_lci_fsm_global_esc 181 200 90.50
otp_ctrl_parallel_lc_esc 58.380s 26902.262us 181 200 90.50
sec_cm_kdi_fsm_global_esc 181 200 90.50
otp_ctrl_parallel_lc_esc 58.380s 26902.262us 181 200 90.50
sec_cm_part_fsm_global_esc 184 210 87.62
otp_ctrl_parallel_lc_esc 58.380s 26902.262us 181 200 90.50
otp_ctrl_macro_errs 27.120s 4663.594us 3 10 30.00
sec_cm_scrmbl_fsm_global_esc 181 200 90.50
otp_ctrl_parallel_lc_esc 58.380s 26902.262us 181 200 90.50
sec_cm_timer_fsm_global_esc 186 205 90.73
otp_ctrl_parallel_lc_esc 58.380s 26902.262us 181 200 90.50
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_part_data_reg_integrity 215 300 71.67
otp_ctrl_init_fail 8.520s 3579.279us 215 300 71.67
sec_cm_part_data_reg_bkgn_chk 22 50 44.00
otp_ctrl_check_fail 35.310s 3036.605us 22 50 44.00
sec_cm_part_mem_regren 12 30 40.00
otp_ctrl_dai_lock 37.750s 5341.677us 12 30 40.00
sec_cm_part_mem_sw_unreadable 12 30 40.00
otp_ctrl_dai_lock 37.750s 5341.677us 12 30 40.00
sec_cm_part_mem_sw_unwritable 12 30 40.00
otp_ctrl_dai_lock 37.750s 5341.677us 12 30 40.00
sec_cm_lc_part_mem_sw_noaccess 12 30 40.00
otp_ctrl_dai_lock 37.750s 5341.677us 12 30 40.00
sec_cm_access_ctrl_mubi 12 30 40.00
otp_ctrl_dai_lock 37.750s 5341.677us 12 30 40.00
sec_cm_token_valid_ctrl_mubi 7 10 70.00
otp_ctrl_smoke 12.970s 650.023us 7 10 70.00
sec_cm_lc_ctrl_intersig_mubi 12 30 40.00
otp_ctrl_dai_lock 37.750s 5341.677us 12 30 40.00
sec_cm_test_bus_lc_gated 7 10 70.00
otp_ctrl_smoke 12.970s 650.023us 7 10 70.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 413.100s 69778.416us 5 5 100.00
sec_cm_direct_access_config_regwen 18 30 60.00
otp_ctrl_regwen 15.360s 3765.739us 18 30 60.00
sec_cm_check_trigger_config_regwen 7 10 70.00
otp_ctrl_smoke 12.970s 650.023us 7 10 70.00
sec_cm_check_config_regwen 7 10 70.00
otp_ctrl_smoke 12.970s 650.023us 7 10 70.00
sec_cm_macro_mem_integrity 3 10 30.00
otp_ctrl_macro_errs 27.120s 4663.594us 3 10 30.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 77.690s 64862.725us 0 1 0.00
stress_all_with_rand_reset 5 100 5.00
otp_ctrl_stress_all_with_rand_reset 114.780s 19267.165us 5 100 5.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 98 test runs
otp_ctrl_smoke 27404306046650217476836260570805975749542199178503162251430437801612490716093 1794
UVM_INFO @ 81180445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 34001031163043684661395615432482147799167983971394754029596223275412439162526 1301
UVM_INFO @ 185550918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 112341714651768685790285998081558584404232334839932419498636722517554176236398 233
UVM_INFO @ 545077164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 104808685884175971188541897948494175028787108359932701818434886632875527892356 2062
UVM_INFO @ 96780777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_smoke 76512792404035998949749112440210621302448594611905309623180407465492660177866 7202
UVM_INFO @ 354937391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_smoke 61188537016641897931848326381153509415727573809019206743961717012948550211330 8874
UVM_INFO @ 359475221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 95439295872677681974607953088191126413756584164848228658555718612982541030159 9130
UVM_INFO @ 3765739463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 53581267441518863115751579465555649183324037635937673369665144205532482841857 99
UVM_INFO @ 126101760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 6744407259006168607534218277805171610668448318742423486819319455259779554501 3066
UVM_INFO @ 290424026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 24441932990652003863683459080329000249984619112254656299416840882254313827537 1920
UVM_INFO @ 82472058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 10616452557787674949558606155302695482975879722283093544366429100859859290701 2666
UVM_INFO @ 123636823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 54900717084854613384293547725842225011150510194017341468448301483528043471533 2655
UVM_INFO @ 299054913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 30734670972627674063474010288454829887778294958553925838049784764715048631559 835
UVM_INFO @ 69432013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 68389689106886041743199157711266217834136912390405492237811448889674809906323 2948
UVM_INFO @ 91685107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 89450661764307008559716555844867170260492821100082263802757414888610300853692 2252
UVM_INFO @ 128634149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 46250210620547702423836214870398822095130379426698344602002523895773100737383 1703
UVM_INFO @ 109145066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 102490733180303340043287402171414094309772102385026980260155917883538179740840 6790
UVM_INFO @ 3631056064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 30029876299048429931055177190999000801838035311312446321775355059023862995155 2910
UVM_INFO @ 1286915462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 646624316738646728066424311045255818529819542133487568867997873349312993160 972
UVM_INFO @ 664567629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 22864121705630213837046694375233296305925455473835651367575308016306905073642 691
UVM_INFO @ 79164133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 39009991843301037774467636069091756120514507394211016680736845796082987262858 7848
UVM_INFO @ 3544637427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 98889323831401986157551839494898408367147577081587000855823096273837181791400 1920
UVM_INFO @ 119970745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 14509202120116806385096860732927552690004167669916231937009944545768448526094 2637
UVM_INFO @ 156427080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 112036590039518893768859884499616406723276163193465271785882977226841666489257 669
UVM_INFO @ 104803348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 104364403990285346129401419546708053798687632930533247585990923495379978478801 1757
UVM_INFO @ 77692721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 67692100072645117894596227557897859216900326406017144123184457345003928476722 921
UVM_INFO @ 87357055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 74434655862922992607257037808748186767475128666834483802456196675515166637335 2331
UVM_INFO @ 78618555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 92117591866881405474264087168572976587249656375944122864682339051623547023919 225
UVM_INFO @ 793522100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 101267883983610731904518132043682324417434457768539632793646109264441464707719 1617
UVM_INFO @ 77749741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 109115617672443919857536620143062932157101773912557015046824601061544557392971 733
UVM_INFO @ 157490347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 42377171083864824438083643996143097019821775634329919176326958013896775542560 855
UVM_INFO @ 681520890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 43142540140552515078235670210669344101176778844723540850185313827719564691935 283
UVM_INFO @ 174805334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 89125033575888930742624856621795112991659355320756811348220611344582491315932 551
UVM_INFO @ 736223750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 87280266811676921124213457937424762972118057081189867516946268942727036371469 241
UVM_INFO @ 79699557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 102521920891170399313758871291524270030250998513012541373584569937589860556909 1593
UVM_INFO @ 58033927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 69542385692250954160727442648148474648684642941910563580568016488777422448940 669
UVM_INFO @ 216453226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 11814106249128270629640662800198937792811027180227307036695629628536445832220 99
UVM_INFO @ 515658877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 81328604581730605590133282570195221077394696593626276872591298085331463072985 871
UVM_INFO @ 86874125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 69842015577199321515643258959941941332878924982360983904154007991800636030801 1489
UVM_INFO @ 83240277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 6321266954046560747062902264731139278030511175327312808203558130455324301489 535
UVM_INFO @ 222401379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 22181692078710178290934019206307901633554649034333385259799941818534218587754 365
UVM_INFO @ 62563849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 8354188065836287220471714366392099942984535602999093682402251129393094606993 459
UVM_INFO @ 71316458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 31278232291468422832340298703170340116403510854995749673068331071342576894936 443
UVM_INFO @ 170790385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 93419579473717117006605228010670773826195470512668123963631501782988592140915 459
UVM_INFO @ 65492520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 32829130500597301308660799895633577989034532876518999431223834414021624196545 2271
UVM_INFO @ 287649000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 41660590238420088505239219512918074288263685923154433161986511148474904850412 941
UVM_INFO @ 97307513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 93772366718245809749020701526211400454174055934076308167950938831900333119255 1851
UVM_INFO @ 1327239083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 21376860947026436444450422070001487588203596989368177551102078549980840691905 481
UVM_INFO @ 103581614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 14732978425505849778594645374579784862979691890128404058579472944127149491562 99
UVM_INFO @ 64332873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 28403249404281600977246429397419401896594151759701348404712722915392111116974 187
UVM_INFO @ 69543857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 102045129078873299498387231035818876713346305221585156068730681882897905657794 1947
UVM_INFO @ 147323296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 92373617925604056049344191080990132176796829450062622394424883777591870132418 775
UVM_INFO @ 41264492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 10304822685514460870023407296368538885713201555382548409730437822008354277692 491
UVM_INFO @ 57005887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 60317901255182330807040586021021719805651845147538635953691850426089726281433 141
UVM_INFO @ 126168678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 26738863989986072788075474484166926875236802925577998131837213588121622277507 799
UVM_INFO @ 137809212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 27130214256687896930607093194072105154041832358035551670798611522372253665389 99
UVM_INFO @ 32898823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 12521288149167178305362801609240943105118762784089193263570332966599058746864 225
UVM_INFO @ 32195070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 88605276065346336771674916570113221229986725199945054630301596026682426552928 141
UVM_INFO @ 32917029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 106791951180356209450705215736023071150697931136145540852386013756106157849425 187
UVM_INFO @ 156983747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 6946767145303322475153678301449187061699632571827926944833268009478266365531 389
UVM_INFO @ 54197246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 114680807461850091859384683452789758973042799874621919383257768168736324533619 543
UVM_INFO @ 179728725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 103819302400818601660562753904101223509466674201214155539735159265803952268206 959
UVM_INFO @ 707849434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 42236728242017661061350538660939609585564976849134130868367235245912184979618 1735
UVM_INFO @ 95381609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 26244107356048656596430724419534246625640725916265887386886366131509595387598 283
UVM_INFO @ 180603902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 30726264919803380961271722759360057729552985372516099545944242856857845315593 399
UVM_INFO @ 39527224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 36427647660360604738973872735407269825673215093139601054826956590789518806578 1121
UVM_INFO @ 224692412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 29154044993717434341996750133501085739422670320758063817568992622682471756216 2233
UVM_INFO @ 182547850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 25666765086796013433510015747454891488742246046774289422806717965854433646895 99
UVM_INFO @ 41544752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 81495270718416867749748778360212123267944190358928845868109957546300549364537 463
UVM_INFO @ 35116175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 41378890053935976072301163637811499877883446171476033241866117938262518198353 761
UVM_INFO @ 49253701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 102524889163120131566700493406765084847254248320604816179539988098382010383804 899
UVM_INFO @ 48874683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 106517490358420306826879218276981567061466798494664084449525551494006733363319 413
UVM_INFO @ 101053250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 9924791675527588588421649947763147952478965330164888928716200838158456331909 1519
UVM_INFO @ 92268298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 112500069429099008247117909964192507373200587012211888980742185375114640378090 1443
UVM_INFO @ 102173614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 53486947151931279844135999835360206836065879168417554826009440422099413258391 1703
UVM_INFO @ 1116272940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 19769596442029436118015188749623286393882207114332766410006198958644743343560 1877
UVM_INFO @ 130435292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 67426306968573581635565495493156284992382249877826325787018051524773679314279 711
UVM_INFO @ 79909977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 13197378799133679708754075932998562905036368825626669293042451236785207295728 899
UVM_INFO @ 133187803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 47471901516575435196406862587167029462202055265812253128288914218357387098296 1163
UVM_INFO @ 95973394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 86449802152963337432643162106083024514557579724335383917705067665742465224182 1419
UVM_INFO @ 196677226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 115339449015108686539462322564806484592236534602169554045043185555020751537569 341
UVM_INFO @ 47080891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 26371654217307295691552520639483122494906593372718783224612826529975946052571 1205
UVM_INFO @ 60853712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 101534752408396763641038598080160223015636626544215561589634842584155099741112 1391
UVM_INFO @ 112356631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 103928865877626269990817086787729830475576032017009044415550668393242864199211 1781
UVM_INFO @ 223297994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 65411585539668895641624072247411839073527811206545672946267396043772666547610 1835
UVM_INFO @ 106995603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 34735283798590781429517459225643075003245539021613500199084046155198584183718 149
UVM_INFO @ 508541669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 92779887243331950095635231928794485727675165665943796693515045402206463437401 1717
UVM_INFO @ 928324014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 3245588635031628315615115183225244551605335670959268685070822791743811695162 267
UVM_INFO @ 61328629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 104948850146166137934248610216383721461432185005972863331512701848305311311182 625
UVM_INFO @ 158691163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 39648493450693047337956684424309328897231032599110529912518040633037214077141 311
UVM_INFO @ 127353962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 26891771120124042815864305944422765990222500276421602320784372230600848177762 1015
UVM_INFO @ 173206693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 77471345357457869642232755272909144011364103352094123471890432033751912260442 99
UVM_INFO @ 516449900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 6917765289737294119773127588968242378674559309925627645812911871750806398791 1267
UVM_INFO @ 121391742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 22624905682938742477712104237403205518215945524633057057012950453300333061441 775
UVM_INFO @ 44324782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 34329248427792326244153178292776372611955725637330321740491136075803731990549 683
UVM_INFO @ 75239297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 104313402700468999506676774192694237129924852895737547850501698274925564026336 99
UVM_INFO @ 194678202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 96522014168220928219836901741487310270837816455328394018451560689177170845740 359
UVM_INFO @ 63807981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 18988350030008968385038948323171321466244206499999068080361136595140016355634 1521
UVM_INFO @ 221539745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 77 test runs
otp_ctrl_background_chks 76421802458609000726481813789802673804917315147224192232156710005669774594809 5120
UVM_INFO @ 3326488683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 25629088866689107563370137354449595426505908386950406815634365119979817501658 2640
UVM_INFO @ 123122335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 90884194163040333558557564144764415051600084543754203102868615669850509628186 12798
UVM_INFO @ 4663594124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 19194024846236944692304213142691166888520553179669636699726021540016101949295 2549
UVM_INFO @ 1149735074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 79086204672611253957648356017041323514879784791748607041703252147520939061424 606
UVM_INFO @ 1294478086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 89143525761166832038550113306777600532591926826807549460326989533886504977020 3327
UVM_INFO @ 258155114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 7048361658340099369273590797635370605947170107424682876347073639603312729843 5909
UVM_INFO @ 520451067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 57912521530874049353842023202668388043445236314163822809199895971504307008138 2808
UVM_INFO @ 394433346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 94914594306742586381225533896154845947191514461859721516300828904740251911176 4206
UVM_INFO @ 83329118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 87858896005850718424704732584910730927922069969250797827919575275488544133247 4984
UVM_INFO @ 87815276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 109645048328749789180347220711363008122921950775581087314499853171497866379841 2072
UVM_INFO @ 157798269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 41942779166621199441760469780876389305135862171535368244371439946001963542779 1107
UVM_INFO @ 665875795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 99019495232505270080158306857585533990973180874607607587773450442916518249580 6719
UVM_INFO @ 320370494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 58720070278378170751076888656055810051809251133792997504151046549782159694065 2291
UVM_INFO @ 483327698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 92519650727251422203170495793434741269449660960919580149379600758203328388072 55063
UVM_INFO @ 6238277406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 71751386008873399025534864744299322908732189071248220818788385846469085684231 4176
UVM_INFO @ 4955670008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 8702861309223582516396525911554716778803325073857821901498941029442443770190 4692
UVM_INFO @ 146018116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 40473108044971521885672152106943214316678187822033317753497888724779566150903 6803
UVM_INFO @ 858549595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 81528693710403310848741922027904070492878888810826898590920140947992977480324 1031
UVM_INFO @ 617266068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 25897777017100186403708199697831728143365274008558034024303434954311480076209 1160
UVM_INFO @ 350014775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 91406034925948240191656618745992994518631444299605091830009748586598627876435 162
UVM_INFO @ 50219401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_req 102170129112501285804849493432465195666779598026067435621422540498859412612230 1888
UVM_INFO @ 243147444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 57386482482320876313503353404954698082617224035194838605076046370465748905179 3310
UVM_INFO @ 318206592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 115197366718727003919900956859099911255740947957319740563439290388581995697669 916
UVM_INFO @ 40620495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 9076317677493279276227173077799940461426502821269809706466716839601888869345 2292
UVM_INFO @ 225357420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 97468213811832107681284900257272281644313253169637974251045660413806327059231 6603
UVM_INFO @ 187666389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 31679624304817794823043640899783270539065327337574087453495680031806778298238 2902
UVM_INFO @ 361634128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 60915201411780583469692364817661123864542547613618457522661529580841906145886 3720
UVM_INFO @ 200162769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 88502260799565849945366121827548040499343735203475070285783494478273268813987 2022
UVM_INFO @ 430128856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 80997860982823310978258180224260314935065576503758217131820003802881840761242 7148
UVM_INFO @ 848082560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 1101973123606978872624411872969777735498757436767484097653141085785606261483 2910
UVM_INFO @ 153683358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 83324426335545333301601766126115476422929700955656444144465572580100490506040 358
UVM_INFO @ 47128062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 30732632542086934487123419368390569994568478002513637740571810322135048688940 2808
UVM_INFO @ 1050364959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 82676023109985874661482027949476195448468950483184771478061853625864139576198 6787
UVM_INFO @ 681511564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 83656096117459394125206302981914566113555029590549228086491846616633588425817 15511
UVM_INFO @ 1593583016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 58816043938090048688271999526318869196149319829046601362030889303076475978133 976
UVM_INFO @ 172676633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 12229214298262969534272812530269828507028963310656878503663647604594661807280 486
UVM_INFO @ 263630908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 90310094456248974615712215045038311862684108945047645784690177905543419473669 2446
UVM_INFO @ 165781454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 66598526850489455531833989691663006615006412525998292252709650356606567455016 17908
UVM_INFO @ 1461032799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 14217607633520271894394748038276136524190297555582185287386514019343508903760 7863
UVM_INFO @ 1106454003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 11957126088336129639034848422370851554937747372695391047103323935320146794998 648
UVM_INFO @ 91588192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 16331712234303010643116282689733493746507186064403803755077451747518685282679 2276
UVM_INFO @ 338420337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 111691285873047102460760960814623514677093941816607032508825604586657555423823 3984
UVM_INFO @ 179287213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 106967692698661853590541429799950012518192955703539282750126211175763919728775 4808
UVM_INFO @ 405610015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 92004385871031543036423097302429058163152067721709250856443148098852938218592 3438
UVM_INFO @ 161707311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 60547821450042715891883783981221946973608989333902996481599167615621248532932 42895
UVM_INFO @ 5227641660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 60333430471003218926243341322990038632283543550628894142681064056216886601121 1404
UVM_INFO @ 102039249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 51635863671302583660260356807833138276588163360711538847664569566803092892066 3662
UVM_INFO @ 278002634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 54802327266796841910666940476986927243044989858244364996848801618641618401417 3269
UVM_INFO @ 1487404738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 57640038934687168393920935607752147300015966622854432031857140228942200882994 564
UVM_INFO @ 103916143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 99447284353615444765689563851922609304985507574137142914574680484151783076141 6834
UVM_INFO @ 490247935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 77240041140730557705560866779838373491514244933044737947247610657091292852858 19873
UVM_INFO @ 15266425860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51295804843287439338585259217574152832828390666252315322197865866267750471186 2319
UVM_INFO @ 1846813454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 39183597387975661977543921283487007929357715307228300744891994545256729895971 160
UVM_INFO @ 184220930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 76233067586761638455022748011178958328463131931710877333861612369445335026646 3536
UVM_INFO @ 116682105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 50668001600740698160827669954328329204749641551520629569236443023380182145600 3557
UVM_INFO @ 1207587166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91745145179321872243638380375835686074080262390151468103351773841585626729366 36153
UVM_INFO @ 2030065932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114698480850153370288003763762773233700458512510796661831329526051048234495620 10061
UVM_INFO @ 5627519105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 7707007861506970362865193786140830784017085786212654013743878564097665423513 8938
UVM_INFO @ 9523391811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 94514283147185161117159968245859944284451089223248112945834541563675122318374 3158
UVM_INFO @ 153117971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10178913846320426772814814451490064466624925712182506601406959156943689765109 1118
UVM_INFO @ 117404115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 89703020705542400618410337047495516108389498654930947294414418364378295022161 4324
UVM_INFO @ 1134501140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 58874084383734932406670383545492002775353444516238884746082717733590409419415 2706
UVM_INFO @ 3190030558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 27083705569884172375382427675337200227866409661750507358063580571637873438939 11448
UVM_INFO @ 14805010366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53762338474260047909122487897674053233003762358844432902151522883816693176930 912
UVM_INFO @ 360799250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 110629266322172099744394775401610442402652144528762047372722364210099283959561 1396
UVM_INFO @ 393332065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29748332917019740594416930304496508145436045747271308435865820333770724572021 16387
UVM_INFO @ 5344943386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5223267978563962959966770064616654569010253631594653658253185197488534556685 4903
UVM_INFO @ 3439644226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 32400090264947464418758936069912149429134821228567709677230516123708198614764 1120
UVM_INFO @ 1404248073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 106800729529963497268698603768767851607567748335020761258688534027151545441156 4880
UVM_INFO @ 1780839954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 92945129358000212700589946186681520910528195277343104219137596862060533768083 456
UVM_INFO @ 52176742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 32860301330955042078286186825475801222004323302758563519669533605986154716994 214
UVM_INFO @ 199933235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 10885456697495355336590208523415519372002028763206231105532248557638820935553 3046
UVM_INFO @ 149959701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 84320347141012148897233905194797346008120916401765311036465246813158213578938 844
UVM_INFO @ 1272971999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 82598878594143389241361615769235181005922886270161124435288394460710250341697 598
UVM_INFO @ 1026809824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 96387305455724973463532029419546285272577076963990001809550276331256871703392 2024
UVM_INFO @ 839153706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 107205733047105054959676715421762423142496542727631234654535237519014130257597 3888
UVM_INFO @ 86356628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 33 test runs
otp_ctrl_test_access 101624135295149958115248048744439466829876121621581736080014872351178500225302 18710
UVM_INFO @ 503979952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 6821672517334844118719146520279146468244617902125710771136219666355870688957 1759
UVM_INFO @ 2739151297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55720273549871706888900082339777267750113830486061288476443788982743036438225 246
UVM_INFO @ 76312510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 40475876385371230568581805495740677999240314097980354604515771369740352733147 618
UVM_INFO @ 380488988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 58626146276463112606404014733248602373791813138317616981839501865228256610178 1658
UVM_INFO @ 586806306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 62577283576117354744370970455611558596289806212396846077656005466541969778552 22982
UVM_INFO @ 10021758593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 37144810711710397024655071042269503024530741000148403646113473455707955718523 8783
UVM_INFO @ 5664079151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 49836744726629765213424036948822317183181091478843765267976574194094035338857 8291
UVM_INFO @ 1127919974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 103840130328769924505055540490723682309965065197290526036733641491595140555191 4873
UVM_INFO @ 703975507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 38594463759267439841055464146227017541948785514243865917730582531863383425069 24342
UVM_INFO @ 7498086750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104676149193521455590898081132508240661952846657752662786075384065148129731388 3832
UVM_INFO @ 134885124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95910799799197366481096418074436659463482278888838401297519042227562992673245 138
UVM_INFO @ 89887795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 66761764018421903409753211836734807178296762944847878644968112040324747536820 2089
UVM_INFO @ 559527031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 32639687199640997922850021365635991637680072130964861415132696445492592941896 1682
UVM_INFO @ 567452738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 88568803500160214336480395004748041826706377296517227724163879793785464006456 29287
UVM_INFO @ 3623091777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2915763413351595679827670723962856212437142684838185679215285717770215667157 2180
UVM_INFO @ 1124333441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 49288426343031063886458471252971394353276367372040108328905273503912826703346 2929
UVM_INFO @ 265097293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29205287435495140540009343700167832359016811172902838052816647606678728265644 15572
UVM_INFO @ 545882756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76735736447225074090863431677478193669022234304997244616628131716551483542960 15153
UVM_INFO @ 2617849212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55949842989574007798354019419433035897713090321607298076399519594115017817552 2523
UVM_INFO @ 353617777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 92789938829693062600586833135266472789723515152037867954034983133133678878308 6916
UVM_INFO @ 8316213511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48130384130712446931291444815115833599065186009957242611652257000146132108022 3706
UVM_INFO @ 2185648902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86678646624892507792073271750683723554866975001331555775630824744903353215291 174
UVM_INFO @ 77387113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 19250822339663204643913190031311392278715563743572010086147622504644076632129 7814
UVM_INFO @ 19354484850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 100160303100087333505161088764974575898286534928117590990307732320006746160145 347
UVM_INFO @ 713032304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29676455986818488922402026258044420922452907204727839435843431010843034319895 881
UVM_INFO @ 510779616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76530574100128978113549703624242078390712541987749215978616232599153474782653 2599
UVM_INFO @ 4400554081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35859323071293739443831817133465120203717399005868112398555230016687029709042 26735
UVM_INFO @ 481759334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5989023104861550678432399192255496567546487258538915072290074989361935481316 3216
UVM_INFO @ 898354090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 77624667487101139685533078245842403145072530379231013443775549721734817841483 2720
UVM_INFO @ 837055748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85640044491079918953069335753693965321294799443408428252629345272460181297693 170
UVM_INFO @ 101912847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 109102317396788903089959171408614846713239111723799437086952590392282494441753 10985
UVM_INFO @ 2866337941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59639227980873438532938008395339808569672432124994873708939446154646771633041 416
UVM_INFO @ 80766514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 26 test runs
otp_ctrl_macro_errs 75958538137824327070737372441133629590545915682082418499969494451499894374908 1798
UVM_INFO @ 863802452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 7972434889002237465510066457832505810884829479015674233438410836644199784839 600
UVM_INFO @ 1463979797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 58672271590829792483843211116004905620162704727708452185499230646653417307658 7359
UVM_INFO @ 2335130400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 88745242300019375660844839299772734617656503415199896562307913019106042665038 3088
UVM_INFO @ 3302254799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 56653139384380403096311456043829402253332613501625601995314292894832347726276 7243
UVM_INFO @ 798046971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 104533546071256846809370792197658716491391017132509267209216803218849351674831 2454
UVM_INFO @ 151208829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 13573543748731401904302466384039665279003690493246025993597244316585263512629 20184
UVM_INFO @ 3036604628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 2950618063741695714077571665560165869595368839090700255829015000096605785613 5071
UVM_INFO @ 581283811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 18297051754351105588972689416015874431824511728308649569671683291532807557615 998
UVM_INFO @ 362303248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 80176853947025050443464211369287249436158312467569239631735040143758964607812 16828
UVM_INFO @ 1274065699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 79038338787279653615887937461995011350694689113970827806501923630345898244288 6701
UVM_INFO @ 4084016034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 105011893707211889532099094452513356808468861121092582706122310009163359886064 4926
UVM_INFO @ 6987292554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 8010430187733300638305496562356969367018254043191686545470300219242238405366 1765
UVM_INFO @ 4515221809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 35736096283648144744372511339798017797102300063874606590028737171857622760342 2572
UVM_INFO @ 61357134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 78205350823080747947042996300366035622849774201507515313657575253962752346703 1278
UVM_INFO @ 246223364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 1211418778502629847628875898156245591038920004785564691855107922760095540566 21016
UVM_INFO @ 1789537492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48328125450063012322948769266340018926011596637591105282381096441004184229893 3132
UVM_INFO @ 1390990274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 63244469617691025351475289737843058427334909946163209113570451113770712932257 8393
UVM_INFO @ 1976361224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 64390838630490083021020045552595552096335382483229895817768947383860882939161 3845
UVM_INFO @ 1783150050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 85852881771704245876230363911102363983889269554576811334237256478647408112111 6203
UVM_INFO @ 7876056151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 64426323751246371577753066194273600149094637501991170670882087790442554507152 6403
UVM_INFO @ 2518751420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 47842074801490392068723378645548432621467926670775659446868295274059522994309 5918
UVM_INFO @ 456716690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42319724478132971189856728618474734331609666410386066726158972035528835499524 172
UVM_INFO @ 72934733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 95413198870261116994688818996658233058730261829479626149532277413899159994954 2084
UVM_INFO @ 296701864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54876078816179025347417653205165316589672672611765693677849441225357646066221 5049
UVM_INFO @ 16364083669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 58491770155830292500057829003624450501981082057559263398137504284727480558263 5060
UVM_INFO @ 2200652443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:2213) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 22 test runs
otp_ctrl_stress_all_with_rand_reset 3199715476878661512065715834378157035590464510114193264889540479127853562277 66419
UVM_INFO @ 5754393372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73404109447439267078747766758238951558645821995254344734460547699750864333037 18408
UVM_INFO @ 1745582124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 89276551892822933404875344960852269706086269711940274954580650390558042995220 91
UVM_INFO @ 65259384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 37163051982473057936240113768024381682925448678504226420925858064479191897854 91
UVM_INFO @ 39973738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 96227551738970074688910103014341334863626025561461230095866454176250723999187 1697
UVM_INFO @ 158865604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 11274290804244085393903914874834311587475532702581043651683515480335436782261 91
UVM_INFO @ 32875062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 32050623112990675619524508902950251194495404163802265404735981782354912942437 8160
UVM_INFO @ 1171755364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 40389852746801266690317714804026429738682831056939431684665163692492395336497 35553
UVM_INFO @ 10944045206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 106264757221371202148525246268493952280567905233953697367206472123996271156292 91
UVM_INFO @ 67120176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 34855920015706879249070305240351978821026960367780733167300258663874319764947 91
UVM_INFO @ 72124681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 102940656924543484323320522591429877976766645769879762082046729517606805299518 592
UVM_INFO @ 11358362813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13987816502582036258868746691621669833154560752146302012992934007693664583087 32107
UVM_INFO @ 3208308179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59838351611634452926159550711313504745170343093576059740051797936735497190661 92
UVM_INFO @ 62603108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 89710811516107724744071116357759137207459176539085282944015440393372848877815 92
UVM_INFO @ 33629420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 65203849608994029101408716043995641448951876138233711733889717906412378526519 91
UVM_INFO @ 500264960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105809265703305319264564824950518298138350280047316888336883105382172242307345 9907
UVM_INFO @ 1118825844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114980126024249949724289161294180048933350311765909396732230350991973794620256 17460
UVM_INFO @ 1748020118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103174046153296519922295431328611880138995678002601782603108892526958815296443 26887
UVM_INFO @ 12204447143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 107802335251962737421156870664832531072205410666269065108982078780645193519892 91
UVM_INFO @ 501612155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50928931322215660260672248373649439328906355576385088735396700599209606448062 154
UVM_INFO @ 2855937709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 25447835820618766776068493373896026420326904451633756754754855406021225050936 28465
UVM_INFO @ 1277958347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 111082372056299719040636964059867972870387167835128535403214132720952775382205 455
UVM_INFO @ 2261318741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 14 test runs
otp_ctrl_background_chks 46704447224158281209136702811794969041151514080198164681376701503675931156570 11073
UVM_INFO @ 3384343903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 110701930261540297883492741627890406742356962021890890589076174417266533210754 19430
UVM_INFO @ 5109280097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 107631474549600060694541251743799940593430826821307470022794696434562362409466 5212
UVM_INFO @ 2005363340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 60620395218359600136366022570198239587384456439812978443774074689606019858284 7173
UVM_INFO @ 10060647501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 90832733905803878779042573148854840774016280464226417697883289102462988875246 7788
UVM_INFO @ 1288704769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 70340704948842477316803231886726827028201563508840960546027073972826054408179 4382
UVM_INFO @ 1566993132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 52047192104657033383528666516576797497948639007778496433127839359630119428452 10523
UVM_INFO @ 730342161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 23711805989447332496150323923539978249378643726762564973362683765229455591468 3699
UVM_INFO @ 1400993821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 102414823006521206597236533195941941909818721937154661832901390003122091420730 6634
UVM_INFO @ 2795964477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 29196844903748835655622125820371590947709250529192154018077243314987560474085 19785
UVM_INFO @ 459360469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 67789305233083072205244973124439733991114343104874570792266073850106101699193 5513
UVM_INFO @ 2677745625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 69989163058198473226919653287714617750804166561764930427171501765214531814383 20384
UVM_INFO @ 5468858865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 42398279242859561821540033545004111681618743920603662680055951867850301013999 26840
UVM_INFO @ 5341677481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 75592005230515863932697665791778287211597018098974624209647433153207707588770 14114
UVM_INFO @ 5706717682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 10 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 21339367332782682515120099661808425392509670886555278253558170365938366609687 91
UVM_INFO @ 88188493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 36878255552316515881686356611913713631174310145150221761305754753637697278695 91
UVM_INFO @ 36817236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72639998304288551696959858274840192065623583799224937231852178587559945651068 91
UVM_INFO @ 62766483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12438335664363028949706207108164279184055424986057916189346132879056812380507 10663
UVM_INFO @ 9555449558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 16678919782358140019109496304955127563245379018083652491588081148155040843217 4596
UVM_INFO @ 833920317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59151495652622639878975999939821871544076380829827599177775816220098923442494 20648
UVM_INFO @ 23148914904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 89085758995556777949980482318358785746731733370512077152613068262092814320890 45478
UVM_INFO @ 19267165425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43816921438577798079792983892426588248594346631856829751827259913813764199595 5242
UVM_INFO @ 15594587230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 66832386101190123552738968514373318786810163550163541337143248165128163569565 222
UVM_INFO @ 3256378541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 30737752497570070593242505266957370910901245420006404020703116361817894312328 91
UVM_INFO @ 65731029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * 8 test runs
otp_ctrl_parallel_lc_req 13343214416646543032177128135317445520715519340543782775459200820905447973489 9524
UVM_INFO @ 333270202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_req 82915892152365970399590572373760663405201882976661774597150298345223749382714 21831
UVM_INFO @ 1645066073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_req 108096875336492912447799870302105616217338058267169212952604075799456224438714 10199
UVM_INFO @ 441633213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_req 21846716484546164617926193933325169909844212994653423091678333838875266596866 13618
UVM_INFO @ 600254523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_req 92601801321892117950906352518949202093517619009006075567124215479396526296625 5289
UVM_INFO @ 278649095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 74827456142750965360506982704155468658245787979332951567293428511968327608287 31490
UVM_INFO @ 755952345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 103300245700254914128359131584858735233394045444987541187047557872224251560123 6501
UVM_INFO @ 1310321538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50259842164288089950420037432567249196202721765532399250141398513139086970960 33542
UVM_INFO @ 14437581593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 3 test runs
otp_ctrl_low_freq_read 90856172143259262951160892811375022999576888635317135338388234074128571581486 89
UVM_INFO @ 64862725281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 25787187677919657175862904595554522544221118426980081947443342681828209540868 90
UVM_INFO @ 22188011590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 99760193178829510810287778337070095279307815987626839047802211975349217989482 90
UVM_INFO @ 22375635335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed 3 test runs
otp_ctrl_stress_all_with_rand_reset 87493011848238698022759608029990384326857581837425695294065288515102928046103 5614
UVM_INFO @ 1513977288 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 1514122026 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 1514200974 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 1514227290 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
otp_ctrl_stress_all_with_rand_reset 23834069320720334273562604120679255998159598805763634113877257380785114383899 15590
UVM_INFO @ 3505982733 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 3506062733 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 3506112733 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 3506142733 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
otp_ctrl_stress_all_with_rand_reset 104400456274924882709855078555331142468570223374788097410659383820785108007230 18571
UVM_INFO @ 8055208457 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 8055408457 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 8055448457 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 8055488457 ps: (otp_ctrl_scoreboard.sv:566) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen 2 test runs
otp_ctrl_stress_all_with_rand_reset 65950494677649814482918322370144729206490354437747444411167872842860491477397 8491
UVM_INFO @ 23123342071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59697805994891463426857425234410887167868572170780274216818961914372588804267 3453
UVM_INFO @ 23845607888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)' 2 test runs
otp_ctrl_stress_all_with_rand_reset 51142548836550679377072250616969351087564336764602557375285583588012549067744 11466
UVM_ERROR @ 6297932314 ps: (otp_ctrl_if.sv:389) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 6297932314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35854813612504987655099815614347981769383765941754580968918688346204446380192 946
UVM_ERROR @ 426402551 ps: (otp_ctrl_if.sv:389) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 426402551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1365) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! 2 test runs
otp_ctrl_init_fail 41748526775587037226668531070161572683295782081165171132240687923996576444718 1404
UVM_INFO @ 181345954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 38151882578334163830128070333417397034962064310011822944966078140082914792319 1564
UVM_INFO @ 397272062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch 2 test runs
otp_ctrl_stress_all_with_rand_reset 28476285159465207339652737168666121387871410054523675484984550299064964914977 4918
UVM_INFO @ 11016676584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42684048834538493181647117232519803866716889902309658081490030932502730339748 1559
UVM_INFO @ 13961498557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 15387527582559579357344901611768945527531001982286788727594046816954759378349 113069
UVM_INFO @ 105540085070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 8630874754161385952706592241962745429640265307148941148600212860742568535323 56640
UVM_INFO @ 10590510285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otp_ctrl_stress_all_with_rand_reset 115172256674904010313068621572778950173606971180582206919128634122672587063618 20356
UVM_INFO @ 72652728683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c* rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 14243403343530670532871100770411450917761265486119395754084918980902758005554 96
UVM_INFO @ 8910729637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---